Power Consumption in Cellular Automata

Author(s):  
Georgios Ch. Sirakoulis ◽  
Ioannis Karafyllidis
2011 ◽  
Vol 403-408 ◽  
pp. 3392-3397 ◽  
Author(s):  
Ali Shahidinejad ◽  
Ali Selamat

Quantum-dot cellular automata (QCA) is an emerging nanotechnology that provides faster speed, smaller size and lower power consumption compared to the current transistor-based technology. Adder/ subtractor is a useful component for the design of many computation systems and functional circuits. This paper proposes a practical XOR design in QCA. Then the first adder/subtractor circuit in QCA is designed and simulated using the proposed XOR design. Results of simulation were carried out using QCADesigner.


2014 ◽  
Vol 2014 ◽  
pp. 1-14 ◽  
Author(s):  
Fenghui Yao ◽  
Mohamed Saleh Zein-Sabatto ◽  
Guifeng Shao ◽  
Mohammad Bodruzzaman ◽  
Mohan Malkani

Quantum-dot cellular automata (QCA) is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. This paper describes the design of a 4-bit multifunction nanosensor data processor (NSDP). The functions of NSDP contain (i) sending the preprocessed raw data to high-level processor, (ii) counting the number of the active majority gates, and (iii) generating the approximate sigmoid function. The whole system is designed and simulated with several different input data.


2017 ◽  
Vol 13 (15) ◽  
pp. 265
Author(s):  
Sajjad Waheed ◽  
Sharmin Aktar ◽  
Ali Newaz Bahar

In recent years, quantum cellular automata (QCA) have been used widely to digital circuits and systems. QCA technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. The QCA offers a novel electronics paradigm for information processing and communication. It has the potential for attractive features such as faster speed, higher scale integration, higher switching frequency, smaller size and low power consumption than transistor based technology. In this paper, Double Feynman and Six-correction logic gate (DFSCL) is proposed based on QCA logic gates: MV gate and Inverter gate. The proposed circuit is a promising future in constructing of nano-scale low power consumption information processing system and can stimulate higher digital applications in QCA.


2018 ◽  
Vol 8 (4) ◽  
pp. 40
Author(s):  
Stefania Perri

Challenges created by the trend of increasingly reducing the size of transistors have made necessary innovative technologies to limit undesirable impacts on the performance speed and power consumption of future designs. [...]


2020 ◽  
Vol 29 (11) ◽  
pp. 2050176
Author(s):  
Feifei Deng ◽  
Guangjun Xie ◽  
Shaowei Wang ◽  
Xin Cheng ◽  
Yongqiang Zhang

Quantum-dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit design, relying on its high-performance and low-power-consumption features. This paper analyzes and compares previously published five-input majority gates. These designs do not perform well in terms of physical properties, especially concerting power consumption. Therefore, an ultra-low-power five-input majority gate in one layer is proposed, which uses a minimum number of cells and smaller area, and achieves the expected highly polarized output compared with previous designs. In order to evaluate its practicability, a new one-bit coplanar full-adder is proposed. The analysis results show that this full-adder performs well compared with existing multilayer and single-layer designs. The number of cells of the proposed design is reduced by 7.14% to get the same area and clock delay compared with the best coplanar full-adder. In addition, its power dissipation is also reduced by 9.28% at 0.5[Formula: see text], 11.09% at 1[Formula: see text] and 12.66% at 1.5[Formula: see text] in terms of average energy dissipation compared with the best single-layer design. QCADesigner tool is used to verify the simulation results of the proposed designs and QCAPro tool is used to evaluate the power dissipation of all considered designs.


2012 ◽  
Vol 622-623 ◽  
pp. 545-550 ◽  
Author(s):  
Ali Shahidinejad ◽  
Ali Farrokhtala ◽  
Saman Asadi ◽  
Maryam Mofarrahi ◽  
Toni Anwar

Quantum-dot cellular automata (QCA) is an emerging nanotechnology that promises faster speed, smaller size, and lower power consumption compared to the transistor-based technology. Moreover, XOR is a useful component for the design of many logical and functional circuits. This paper proposes a novel and efficient QCA XOR design. The proposed XOR design has been compared to a few recent designs in terms of area, speed and complexity. Comparison of results illustrates significant improvements in our design as compared to traditional approaches. Also simulation proves that the proposed XOR design is completely robust and more sustainable to high input frequency as compared to other designs. This robustness is highly significant when this component is applied for realizing larger designs.


2010 ◽  
Vol 2010 ◽  
pp. 1-11 ◽  
Author(s):  
Mariam Hoseini ◽  
Zhou Tan ◽  
Chao You ◽  
Mark Pavicic

This paper presents the design of a reconfigurable asynchronous computing element, called the pulsed quad-cell (PQ-cell), for constructing conformal computers. Conformal computers are systems with an exceptional ability to conform to the physical and computational needs of an application. PQ-cells, like cellular automata, are assembled into arrays, communicate with neighboring cells, and are collectively capable of general computation. They operate asynchronously to scale without the limitations of a global clock and to minimize power consumption. Cell operations are stimulated by pulses which travel on different wires to represent 0's and 1's. Cells are individually configured to perform logic, move and store information, and coordinate parallel activity. The PQ-cell design targets a 0.25 μm CMOS technology. Simulations show that a single cell consumes 15.6 pJ per operation when pulsed at 1.3 GHz. Examples of multicell structures include a 98 MHz ring oscillator and a 190 MHz pipeline.


Quantum-dot cellular automata (QCA) is inventive nanotechnology that suggest lesser size, lesser power consumption, with more rapid speeds and deliberated as a clarification to the scaling difficulties with CMOS technology. Physical bounds of CMOS for instance the effects of quantum and the limits of technologies like power dissipation obstruct the motion of microelectronics using consistent circuit scaling. In this paper, a 1-bit binary magnitude comparator circuit is proposed that takes down the count of QCA cells related to the previously reported design’s cell numbers. The proposed course of study involves just around 29 % of the total area as compared to the preceding design with the lesser speed and clocking cycle performance and energy dissipation also. QCA designerE tool is used for simulation and finding the parameters also. The projected magnitude comparator also compares the metrics result with some of the other preceeding patterns.


2021 ◽  
Author(s):  
Saeid Seyedi ◽  
Behrouz Pourghebleh

Abstract Since the scaling of transistors is growing rapidly, the need for an efficient alternative for the Complementary Metal-Oxide-Semiconductor (CMOS) technology to obtain further and extra processes in the circuits has known as the main problem. Over the last decade, Quantum-dot Cellular Automata (QCA) technology due to its excellent potential in developing designs with low-power consumption, high-speed, and high-density has been recognized as a suitable replacement to CMOS technology. In this regard, lowering the number of gates, the amount of cell count, and delay has been emphasized in the design of QCA-based circuits. Adders as the main unit in logic circuits and digital arithmetic play an important role in constructing various effective QCA designs. In this regard, Ripple Carry Adder (RCA) is a simple form of adders and due to its remarkable features can be useful to reach circuits with the minimum required area and power consumption. Therefore, in this study, a new design for RCA in QCA technology is recommended to reduce the cell count, amend the complexity, and decrease the latency. To verify the correctness of the suggested circuit, the QCADesigner version 2.0.3 as a well known simulator has been used. The evaluation results confirm that the proposed design has approximately 28.6% improvement in cell count in comparison to the state-of-the-art four-bit coplanar RCA designs in QCA technology. Also, the obtained results designate the effectiveness of the advised plan.


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