Effect of Gate Dielectric Material on the Analog Performance of a Ge-Source Tunnel FET

2019 ◽  
pp. 675-680
Author(s):  
Emona Datta ◽  
Avik Chattopadhyay ◽  
Abhijit Mallik
Keyword(s):  
Gate Dielectric ◽  
Dielectric Material ◽  
Tunnel Fet ◽  
Analog Performance ◽  
Gate Dielectric Material

scholarly journals Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

2017 ◽  
Vol 12 (2) ◽  
pp. 82-88
Author(s):  
V. T. Itocazu ◽  
V. Sonnenberg ◽  
J. A. Martino ◽  
E. Simoen ◽  
Cor Clayes
Keyword(s):  
Gate Dielectric ◽  
Dielectric Material ◽  
Ground Plane ◽  
Silicon Film ◽  
Gate Bias ◽  
Back Gate ◽  
Analog Performance ◽  
Long Channel ◽  
Gate Dielectric Material ◽  
Analog Parameters

This paper presents an analysis of the silicon film thickness (6 nm and 14 nm), the gate dielectric material (SiO2 and High- κ material) and the Ground Plane influence on the analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices, based on experimental and simulation results. Two channel lengths (70 nm and 1μm) have been considered and the analog performance has been analyzed as a function of the back gate bias. It is shown that at zero back gate bias , the presence of a Ground Plane improves the transconductance in the saturation region due to the strong coupling between front and back gates in devices with a long channel (1 μm), thin silicon film (6 nm) and SiO2 as gate dielectric material. However, for the intrinsic voltage gain, output conductance and Early Voltage, the devices without Ground Plane present better results due to the higher drain electrical field penetration. Short-channel transistors (70 nm) with Ground Plane show an improvement of the analog parameters also due to the high drain electrical field penetration. Similar behavior is noticed in devices with a thicker silicon film (14nm). UTBB nMOSFETs with High- κ material present less influence of a Ground Plane on the parameters analyzed. Varying the back gate bias in devices with long channel (1 μm) and SiO2 as gate dielectric material, the analog parameters present better results in devices without Ground Plane, except for the transconductance in long channel transistors with a thin silicon film, for the reason explained before (strong coupling between front and back gates). Devices with High-κ material as gate dielectric show a minor improvement of the analog performance with a Ground Plane.

scholarly journals Effect of organic gate dielectric material properties on interfacial charging and discharging of pentacene MIM device

2011 ◽  
Vol 14 ◽  
pp. 62-66 ◽  
Author(s):  
Kateryna Bazaka ◽  
Mohan V. Jacob ◽  
Dai Taguchi ◽  
Takaaki Manaka ◽  
Mitsumasa Iwamoto
Keyword(s):  
Material Properties ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Gate Dielectric Material

Effects of the Gate Dielectric Material on the Performance of a 14-nm SOI FinFET

2021 ◽  
Author(s):  
Nour El I. Boukortt ◽  
Amal M. AlAmri ◽  
Antonio Garcia Loureiro ◽  
Yaser M. Abdulraheem ◽  
Mozhdeh Seyyedhamzeh ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Material ◽  
Gate Dielectric Material

High-k Materials for Advanced Gate Stack Dielectrics: a Comparison of ALCVD and MOCVD as Deposition Technologies

2003 ◽  
Vol 765 ◽  
Author(s):  
Matty Caymax ◽  
H. Bender ◽  
B. Brijs ◽  
T. Conard ◽  
S. DeGendt ◽  
...  
Keyword(s):  
Physical Vapor Deposition ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Dielectric Constants ◽  
Gate Stack ◽  
Interfacial Layers ◽  
High K ◽  
High K Materials ◽  
Gate Dielectric Material ◽  
Deposition Techniques

AbstractIn the quest for ever smaller transistor dimensions, the well-known and reliable SiO2 gate dielectric material needs to be replaced by alternatives whith higher dielectric constants in order to reduce the gate leakage. Candidate materials are metal oxides such as HfO2. Themost promising deposition techniques, next to Physical Vapor Deposition, appear to be ALCVD and MOCVD. In this paper, we compare the most important characteristics of layers from both proces techniques and assess their relevance to gate stack applications: density, crystallisation, impurities, growth mechanism, interfacial layers, dielectric constant, mobility. Although we find some minor differences, layers from both techniques mostly show striking similarities in many aspects, both positive and negative.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers

2016 ◽  
Vol 16 (4) ◽  
pp. 3273-3276 ◽  
Author(s):  
Yu Matsuda ◽  
Yoshio Nakahara ◽  
Daisuke Michiura ◽  
Kazuyuki Uno ◽  
Ichiro Tanaka
Keyword(s):  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Low Cost ◽  
High Mobility ◽  
Hole Mobility ◽  
Plastic Substrates ◽  
Active Layers ◽  
Dielectric Layers ◽  
Gate Dielectric Material

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78±0.3 cm2V−1s−1, which are comparable to those of the previously reported transistors using singlecrystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. It is therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

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