High-k Materials for Advanced Gate Stack Dielectrics: a Comparison of ALCVD and MOCVD as Deposition Technologies

2003 ◽  
Vol 765 ◽  
Author(s):  
Matty Caymax ◽  
H. Bender ◽  
B. Brijs ◽  
T. Conard ◽  
S. DeGendt ◽  
...  
Keyword(s):  
Physical Vapor Deposition ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Dielectric Constants ◽  
Gate Stack ◽  
Interfacial Layers ◽  
High K ◽  
High K Materials ◽  
Gate Dielectric Material ◽  
Deposition Techniques

AbstractIn the quest for ever smaller transistor dimensions, the well-known and reliable SiO2 gate dielectric material needs to be replaced by alternatives whith higher dielectric constants in order to reduce the gate leakage. Candidate materials are metal oxides such as HfO2. Themost promising deposition techniques, next to Physical Vapor Deposition, appear to be ALCVD and MOCVD. In this paper, we compare the most important characteristics of layers from both proces techniques and assess their relevance to gate stack applications: density, crystallisation, impurities, growth mechanism, interfacial layers, dielectric constant, mobility. Although we find some minor differences, layers from both techniques mostly show striking similarities in many aspects, both positive and negative.

Challenges in Integrating the High-K Gate Dielectric Film to the Conventional Cmos Process Flow

2001 ◽  
Vol 670 ◽  
Author(s):  
Avinash Agarwal ◽  
Michael Freiler ◽  
Pat Lysaght ◽  
Loyd Perrymore ◽  
Renate Bergmann ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Dielectric Film ◽  
Cmos Process ◽  
Gate Stack ◽  
Process Flow ◽  
High K ◽  
High K Materials ◽  
Wet Etch ◽  
The Impact ◽  
High K Gate Dielectric

ABSTRACTZrO2 and HfO2 and their alloys with SiO2 are currently among the leading high-k materials for replacing SiOxNy as the gate dielectric for the sub-100 nm technology nodes. International SEMATECH (ISMT) is currently investigating integration issues associated with this required change in materials. Our work has focused on the integration of ALCVD deposited ZrO2 and HfO2 with an industry standard conventional MOSFET process flow with poly-Si electrode. Since the impact of contamination by these new high-k materials introduced in a production fab has not yet been established, it becomes very critical to prevent cross- contamination through the process tools in the fab. A baseline study was completed within ISMT's fab and appropriate protocols for handling high-k materials have been established. The integrated high-k gate stack in a conventional transistor flow should not only meet all the performance requirements of scaled transistors, but the gate dielectric film should be able withstand high-temperature anneal steps. Reactions between ZrO2 and Si have been observed at temperatures as low as 560°C (during the amorphous Si deposition process). Various wet chemistries were also evaluated for removing the high-k film inadvertently deposited on wafer backside, and it was found that ZrO2 etches at extremely slow rates in the majority of the common wet etch chemistries available in a fab. A new hot HF based process was found to be successful in lowering Zr contamination on the wafer backside to as low as 1.8 E10 atoms/cm2. The patterning of a high-k gate stack with poly-Si electrode is another area that required considerable focus. Various dry (plasma) etch and wet etch chemistries were evaluated for etching ZrO2 using both blanket films as well as wafers with patterned poly-Si gate over the high-k films. On the full CMOS flow device wafers, most of these wet chemistries resulted in severe pitting in the ZrO2 film remaining over the source/drain (S/D) areas, as well as in the Si substrate and the field oxide. A poly-Si gate over ZrO2 gate dielectric film was successfully patterned using the standard poly-Si gate etch (Cl2/HBr) for the main etch, followed by a combination of HF and H2SO4 clean for removing all of the ZrO2 remaining over the S/D area. This allowed the fabrication of low-resistance contacts to transistor S/D areas, which ultimately resulted in demonstration of functional transistors with high-k gate dielectric films.

Solution-Processed Bootstrapped Organic Inverters Based on P3HT With a High- $k$ Gate Dielectric Material

2009 ◽  
Vol 30 (5) ◽  
pp. 484-486 ◽  
Author(s):  
H.N. Raval ◽  
S.P. Tiwari ◽  
R.R. Navan ◽  
S.G. Mhaisalkar ◽  
V.R. Rao
Keyword(s):  
Gate Dielectric ◽  
Dielectric Material ◽  
Solution Processed ◽  
High K ◽  
Gate Dielectric Material ◽  
High K Gate Dielectric

scholarly journals Simulations of the CNFETs using different high-k gate dielectrics

2020 ◽  
Vol 9 (3) ◽  
pp. 943-949
Author(s):  
Ankita Dixit ◽  
Navneet Gupta
Keyword(s):  
Carbon Nanotube ◽  
Field Effect ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Dielectric Materials ◽  
High K ◽  
Gate Dielectric Material

In this paper we presented the analysis of Carbon Nanotube Field Effect Transistors (CNFETs) using various high-k gate dielectric materials. The objective of this work was to choose the best possible material for gate dielectric. This paper also presented the study on the effect of thickness of gate dielectric on the performance of the device. For the analysis (19, 0) CNT was considered because the diameter of (19, 0) CNT is 1.49nm and the CNFETs have been fabricated with the CNT diameter of ~1.5nm. It has been observed that La2O3 is the best gate dielectric material followed by HfO2 and ZrO2. It was also observed that as thickness of gate dielectric material reduces, drain current of CNFET increases. The outcomes of this study matches with the analytical results and hence confirm the results

Composition Quantification of Microelectronics Multilayer Thin Films by EDX: Toward Small Scale Analysis

2009 ◽  
Vol 1184 ◽  
Author(s):  
Thierry Conard ◽  
Kai Arstila ◽  
Thomas Hantschel ◽  
Alexis Franquet ◽  
Wilfried Vandervorst ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Small Scale ◽  
Quantitative Composition ◽  
Composition Analysis ◽  
Multilayer Thin Films ◽  
Large Area ◽  
Fast Analysis ◽  
Metal Gates ◽  
High K ◽  
High K Materials

AbstractIn order to continuously improve the performances of microelectronics devices through scaling, SiO2 is being replaced by high-k materials as gate dielectric; metal gates are replacing poly-Si. This leads to increasingly more complex stacks. For future generations, the replacement of Si as a substrate by Ge and/or III/V material is also considered. This also increases the demand on the metrology tools as a thorough characterization, including composition and thickness is thus needed. Many different techniques exist for composition analysis. They usually require however large area for the analysis, complex instrumentation and can be time consuming. EDS (Energy Dispersive Spectroscopy) when coupled to Scanning Electron Microscopy (SEM) has the potential to allow fast analysis on small scale areas.In this work, we evaluate the possibilities of EDS for thin film analysis based on an intercomparison of composition analysis with different techniques. We show that using proper modeling, high quality quantitative composition and thickness of multilayers can be achieved.

scholarly journals Effect of organic gate dielectric material properties on interfacial charging and discharging of pentacene MIM device

2011 ◽  
Vol 14 ◽  
pp. 62-66 ◽  
Author(s):  
Kateryna Bazaka ◽  
Mohan V. Jacob ◽  
Dai Taguchi ◽  
Takaaki Manaka ◽  
Mitsumasa Iwamoto
Keyword(s):  
Material Properties ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Gate Dielectric Material
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