Circuit Design Methodologies for Test Power Reduction in Nano-Scaled Technologies

Author(s):  
Veena S. Chakravarthi ◽  
Swaroop Ghosh
2020 ◽  
Vol 12 (2) ◽  
pp. 168-172
Author(s):  
Manish Kumar ◽  
Md. Anwar Hussain ◽  
Sajal K. Paul

This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software (version 3.1).


Author(s):  
Kuen-Jong Lee ◽  
Shaing-Jer Hsu ◽  
Chia-Ming Ho

2009 ◽  
Vol 5 (1) ◽  
pp. 58-68 ◽  
Author(s):  
George Kurian ◽  
Narayana Rao ◽  
Virendra Patidar ◽  
V. Kamakoti ◽  
Srivaths Ravi

Author(s):  
Jun Matsushima ◽  
Yoichi Maeda ◽  
Masahiro Takakura

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