Design of a Low Power Full Adder with a Two Transistor EX-OR Gate Using Gate Diffusion Input of 90 nm

2018 ◽  
pp. 403-410
Author(s):  
J. Nageswara Reddy ◽  
G. Karthik Reddy ◽  
V. Padmanabha Reddy
Keyword(s):  
Low Power ◽  
Full Adder ◽  
Or Gate

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

A novel low-power full-adder cell for low voltage

Integration ◽  
2009 ◽  
Vol 42 (4) ◽  
pp. 457-467 ◽  
Author(s):  
Keivan Navi ◽  
Mehrdad Maeen ◽  
Vahid Foroutan ◽  
Somayeh Timarchi ◽  
Omid Kavehei
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Full Adder

scholarly journals A high-speed hybrid Full Adder with low power consumption

2012 ◽  
Vol 9 (24) ◽  
pp. 1900-1905
Author(s):  
Kamran Delfan Hemmati ◽  
Mojtaba Behzad Fallahpour ◽  
Abbas Golmakani ◽  
Kamyar Delfan Hemmati
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Low Power Consumption

An efficient low-power 1-bit full adder using a multi-threshold voltage scheme

2017 ◽  
pp. 163-167
Author(s):  
Raushan Kumar ◽  
Sahadev Roy ◽  
Arpan Bhattacharyya
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Full Adder
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