Low power CMOS full adder cells

2012 ◽  
Author(s):  
Attapon Sudsakorn ◽  
Siraphop Tooprakai ◽  
Kobchai Dejhan
Keyword(s):  
Low Power ◽  
Full Adder ◽  
Low Power Cmos

scholarly journals Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology

2021 ◽  
Vol 12 (3) ◽  
pp. 5720-5725
Author(s):  
A.S Keerthi Nayani Et. al.
Keyword(s):  
Low Power ◽  
Full Adder ◽  
Cmos Technology ◽  
Ripple Carry Adder ◽  
Xnor Gate ◽  
Low Power Cmos

The aspire of the manuscript be near apply a 14T Full adder unit, so as to make use of little power by means of XOR and XNOR gate . The 4-bit binary adder is constructed in ripple carry adder arrangement. It has been urbanized for little power utilization in falling the no. of transistor. The power utilization be able to abridged by 49% with planned FA difference ate through regular FA. Every one replication outcome contain be approved elsewhere by with 32 nm CMOS technology. The replication outcome of 1-bit adder planned FA shows so as to the planned FA have little power utilization. The hardware accomplishment of 14T FA be agreed with Deep Sub micron Technology

scholarly journals Low power CMOS full adder design with body biasing approach

2011 ◽  
Vol 6 (1) ◽  
pp. 75-80
Author(s):  
Manoj Kumar ◽  
Sandeep K. Arya ◽  
Sujata Pandey
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Full Adder ◽  
Minimum Power ◽  
The Third ◽  
Body Biasing ◽  
Minimum Power Consumption ◽  
Low Power Cmos ◽  
Power Delay Product

In this paper, five different low power full adders using XOR/XNOR gates and multiplexer blocks with body biasing have been presented. In the first methodology, the adder depicts minimum power dissipation of 204.09μW and delay of 5.9849 ns. In the second, an improvement in power consumption has been reported at 128.92μW with delay of 5.9875 ns by using voltage biasing of two PMOS (P1 &P2) along with substrate biasing. In the third methodology, adder gives minimum power dissipation of 0.223nW with a delay of 5.2352 ns. Further, in fourth, it shows minimum power consumption of 0.199nW with a delay of 5.1002 ns and finally in fifth methodology, minimum power reduces to 0.192nW.Moreover, power delay product (PDP) results also have been compared for these methodologies. Comparisons have been made with earlier reported circuits and proposed circuits show better performance in terms of power consumption and delay.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

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