Failure analysis of miniaturized multilayer ceramic capacitors in surface mount printed circuit board assemblies

Purpose The submitted paper is mainly concerned with the cracking of blind and buried vias of printed circuit board (PCB) for smartphones which were encountered with abnormal display problems like scramble display or no display during service and had to be recalled. Design/methodology/approach To found out the root causes of this failure and dissolve this commercial dispute, comprehensive failure analysis was performed on the printed circuit board assemblies (PCBAs) and PCBs of the failed smartphone, such as macrograph and micrograph observation, chemical compositions analysis, thermal performance testing and blind via pull-off experiment, which finally helped to determine the causes. Besides that, the failure mechanisms were discussed in detail, and pertinent countermeasures were proposed point by point. Findings It was found that the PCB blind vias cracking was the main reason for the scramble display or no display of the smartphone, and the incomplete cleaning process before copper plating was the root cause of the blind vias cracking. Practical implications Achievement of this paper would not only help to provide the solid evidence for determining the responsibility of this commercial dispute but also lead to a better understanding of the failure mechanisms and prevention methods for similar failure cases of other advanced mobile phones. Originality/value Most failure analysis researches of PCBAs only focused on the unqualified products from manufacturing, while this paper addressed a failure analysis case of PCBAs products for smartphones from actual services, which was relatively rarely reported in the past.

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Development of Advanced Non Destructive Techniques for Failure Analysis of PCBs and PCBAs

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0332 ◽

2012 ◽

Author(s):

Julien Perraud ◽

Shaïma Enouz-Vedrenne ◽

Jean-Claude Clement ◽

Arnaud Grivon

Keyword(s):

Failure Analysis ◽

Printed Circuit Board ◽

Acoustic Microscopy ◽

Circuit Board ◽

Printed Circuit Board Assembly ◽

X Ray ◽

Printed Circuit ◽

Advanced Analysis ◽

Non Destructive ◽

Non Destructive Techniques

Abstract The continuous miniaturization trends followed by a vast majority of electronic applications results in always denser PCBs (Printed Circuit Board) designs and PCBAs (Printed Circuit Board Assembly) with increasing solder joint densities. Current high-end designs feature high layer count sequential build-up PCBs with fine lines/spaces and numerous stacked filled microvias, as well as closely spaced BGA/QFN components with pitches down to 0.4mm. In recent years, several 3D packaging approaches have emerged to further increase system integration by enabling the stacking of several dies or packages. This has translated for example into the advent of highly integrated complex System in Package (SiP) modules, Package-on-Package (PoP) assemblies or chips embedded in PCBs [1]. From a failure analysis (FA) perspective, this deep technology evolution is setting extreme challenges for accurately locating a failure site, especially when destructive techniques are not desired. The few conventional non-destructive techniques like optical or x-ray inspection are now practically becoming useless for high density PCB designs. This paper reviews several advanced analysis techniques that could be used to overcome these limitations. It will be shown through several examples how three non-destructive methods usually dedicated to package analyses can be efficiently adapted to PCBs and PCBAs: • Scanning Acoustic Microscopy (SAM) • 3D X-ray Computed Tomography (CT) • Infrared Thermography A case study of a flex-rigid board FA is presented to show the efficiency of these three techniques over classical techniques. In this example, not only the defect localization has been possible, but also the defect characterization without using destructive analysis.

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Performance Comparison Between Surface-mount and Embedded Power Modules

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2380-4491-2019-dpc-presentation_tp3_052 ◽

2019 ◽

Vol 2019 (DPC) ◽

pp. 000647-000670

Author(s):

Gerald Weis

Keyword(s):

Printed Circuit Board ◽

State Of The Art ◽

Circuit Board ◽

Switching Frequency ◽

Surface Mount ◽

Printed Circuit ◽

Power Transistors ◽

Wide Range ◽

Power Switches ◽

Embedded Power

Increasing efficiency in power electronic circuits requires innovative cooling concepts and a low impedance connection in the power path as well as low inductance driving circuits placed as close as possible to the main power switches. A direct comparison between state-of-the-art standard surface-mount build-ups and power switches embedded directly into the printed circuit board shows the high potential of integrated electronics. Measurements at defined operating point(s) verify improved thermal performance due to more heat spreading area, as well as higher achievable switching speed. For performance benchmarking two similar versions of half bridge circuits in DC-DC buck configuration were built to be compared in measurement. The first configuration uses standard, state-of-the-art SMD packages assembled onto the module. For the second half bridge module an embedded power path was used: The power transistors (GaN HEMT devices) are mounted inside the printed circuit board (PCB) and galvanically isolated from the heat sink pad on top of the package. Both versions use exactly the same schematic, layer stack-up and copper structure on the six layers used. A slightly different laser drill configuration was necessary because embedded parts are connected by copper filled laser drill holes. This measure was taken to optimize the modules according to their technology. Each module has an NTC thermistor mounted at the same distance to the half bridge transistors, and is used to indicate the temperature of the transistor dies during measurement. To cover a wide range of operational conditions the devices under test (DUTs) were stressed under hard switching operation (HSW) as well as triangular current mode (TCM). HSW causes more stress because the opposite transistor is switched before the whole energy of Coss has been discharged. In TCM the current through the inductor is becoming negative for a short time period and discharges the Coss capacitors of the power transistors. The test conditions were set as follows: 150V, 11A with 200kHz switching frequency in HSW mode. The switching behavior is similar, because both modules uses the same power transistors. Due to less parasitic impedance at the embedded module the turn-on behavior is slightly improved at the embedded module. Embedding as a new, innovative concept is compared to standard technologies. First measurements show that the embedded DUT stays 20K below the temperature of the standard module while running at the same load current. Additionally fewer disturbances were observed at the embedded module.

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