A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL

2020 ◽  
Vol 39 (8) ◽  
pp. 3819-3832 ◽  
Author(s):  
H. Lad Kirankumar ◽  
S. Rekha ◽  
Tonse Laxminidhi
Keyword(s):  
High Speed ◽  
Dead Zone ◽  
Charge Pump ◽  
Phase Frequency Detector ◽  
Blind Zone ◽  
Charge Pump Pll ◽  
Frequency Detector

A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application

2012 ◽  
Vol 457-458 ◽  
pp. 1178-1182 ◽  
Author(s):  
Cao Yu ◽  
Min Su Kim ◽  
Hyung Chul Kim ◽  
Youn Goo Yang
Keyword(s):  
High Speed ◽  
Dead Zone ◽  
Charge Pump ◽  
Cmos Process ◽  
Dual Mode ◽  
Small Current ◽  
Flip Flop ◽  
Voltage Range ◽  
Frequency Detector ◽  
Reset Time

A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.

PVT Aware Design of a Dead-zone Free High Speed Phase Frequency Detector in 90nm CMOS

2020 ◽  
Vol 13 (4) ◽  
pp. 516-530
Author(s):  
Suraj K. Saw ◽  
Madhusudan Maiti ◽  
Preetisudha Meher ◽  
Alak Majumder
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Speed ◽  
Dead Zone ◽  
Cmos Technology ◽  
Switching Noise ◽  
Phase Frequency Detector ◽  
Layout Area ◽  
Frequency Detector ◽  
Lock In

Background & Introduction: With the advent of technology, though the literature highlights many designs of Phase Frequency Detector (PFD), there remains some challenges like area overhead, switching noise near frequency lock point and fast, accurate response to mitigate dead zone and output errors. Methods: In this article, we have unearthed a low power, high speed and dead zone free PFD, which eliminates the switching noise near that lock-in node. This simple design uses lesser number of transistors to obtain smaller estimated layout area of 0.748mm2 and low power of 496.12μW, when operated at 10 GHz frequency at a power supply of 1.8V in 90nm CMOS technology. Results: The simulation reads a phase noise and output noise of -113.142dBc/Hz and -180.712dB at 1MHz offset. The circuit not only runs at a frequency as high as 40GHz, but also compatible to be operated at a power supply of as small as 0.9V. Conclusion: Process Variation analysis performed proves the robustness of the proposed circuit at all process corners. Also, the design gets validated at lower process nodes like 28nm UMC.

scholarly journals High‐speed, low power, and dead zone improved phase frequency detector

2019 ◽  
Vol 13 (7) ◽  
pp. 1056-1062 ◽  
Author(s):  
Amir Fathi ◽  
Morteza Mousazadeh ◽  
Abdollah Khoei
Keyword(s):  
Low Power ◽  
High Speed ◽  
Dead Zone ◽  
Phase Frequency Detector ◽  
Frequency Detector
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