Hafnium based high-k dielectric gate-stacked (GS) gate material engineered (GME) junctionless nanotube MOSFET for digital applications

2021 ◽  
Vol 127 (1) ◽  
Author(s):  
Raj Kumar ◽  
Arvind Kumar
Keyword(s):  
High K ◽  
2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.


2012 ◽  
Vol 29 (5) ◽  
pp. 057702 ◽  
Author(s):  
Yue-Chan Kong ◽  
Fang-Shi Xue ◽  
Jian-Jun Zhou ◽  
Liang Li ◽  
Chen Chen ◽  
...  

2012 ◽  
Vol 45 (3) ◽  
pp. 537-542 ◽  
Author(s):  
C.-Y. Wu ◽  
P.-Y. Hsu ◽  
C. L. Wang ◽  
T.-C. Liao ◽  
H.-C. Cheng ◽  
...  

2017 ◽  
Vol 897 ◽  
pp. 571-574 ◽  
Author(s):  
Vidya Naidu ◽  
Sivaprasad Kotamraju

Silicon Carbide (SiC) based MOS devices are one of the promising devices for high temperature, high switching frequency and high power applications. In this paper, the static and dynamic characteristics of an asymmetric trench gate SiC IGBT with high-k dielectrics- HfO2 and ZrO2 are investigated. SiC IGBT with HfO2 and ZrO2 exhibited higher forward transconductance ratio and lower threshold voltage compared to conventionally used SiO2. In addition, lower switching power losses have been observed in the case of high-k dielectrics due to reduced tail current duration.


AIP Advances ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 065229
Author(s):  
Yanxiao Sun ◽  
Gang Niu ◽  
Wei Ren ◽  
Jinyan Zhao ◽  
Yankun Wang ◽  
...  

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040001
Author(s):  
N. R. Butterfield ◽  
R. Mays ◽  
B. Khan ◽  
R. Gudlavalleti ◽  
F. C. Jain

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.


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