A nonlocal approach for semianalytical modeling of a heterojunction vertical surrounding-gate tunnel FET

2019 ◽  
Vol 18 (1) ◽  
pp. 104-119
Author(s):  
Nidhal Abdelmalek ◽  
Fayçal Djeffal ◽  
Toufik Bentrcia
Keyword(s):  
Tunnel Fet ◽  
Surrounding Gate ◽  
Nonlocal Approach

A Comparative Study of Junctionless Triple-Material Cylindrical Surrounding Gate Tunnel FET

2018 ◽  
pp. 793-801
Author(s):  
Sudhansu Mohan Biswal ◽  
Sanjit Kumar Swain ◽  
Jyoti Ranjan Sahoo ◽  
Anupam K. Swain ◽  
Kunal Routaray ◽  
...  
Keyword(s):  
Comparative Study ◽  
Tunnel Fet ◽  
Surrounding Gate

An Analytical Modeling and Simulation of Surrounding Gate TFET with an Impact of Dual Material Gate and Stacked Oxide for Low Power Applications

2019 ◽  
Vol 57 ◽  
pp. 68-76 ◽  
Author(s):  
V. Dharshan ◽  
N.B. Balamurugan ◽  
T.S. Arun Samuel
Keyword(s):  
Mathematical Expression ◽  
Drain Current ◽  
Gate Stack ◽  
Tunnel Fet ◽  
Novel Structure ◽  
High K ◽  
Surrounding Gate ◽  
High Degree ◽  
The Impact ◽  
Dual Material

In this paper, an analytical model for modified Surrounding Gate Tunnel FET with gate stack engineering and different gate metals has been developed. Further, considering the scaling advantageous of Gate stack engineering and high degree performance of dual material engineering, the both has been integrated into a novel structure known as Surrounding Gate (SG) Tunnel FET with stacked oxide SiO2/high-k and dual material (DM) has been proposed. The two dimensional (2D) potential at the surface and electric field mathematical models for the DMSG TFET are developed by solving 2D Poisson's equation with matching device boundary conditions. Based on the Kane's formula, mathematical expression for the band-to-band (BTB) tunneling generation rate is derived and then used to calculate the drain current. The impact on the proposed device performance due to the variation of different device parameters has also been studied. It has been found from the presented results that the ON current of the DMSG TFET with stack is 10-6A, OFF current is 10-13A and ON/OFF ratio is 107. The mathematical results have been verified using the simulated results obtained from TCAD, a 3-D device simulator from ATLAS.

Modelling and Simulation of Hetero-Dielectric Surrounding Gate TFET

2020 ◽  
Vol 62 ◽  
pp. 47-58
Author(s):  
I. Vivek Anand ◽  
T.S. Arun Samuel ◽  
Palanichamy Vimala ◽  
A. Shenbagavalli
Keyword(s):  
Leakage Current ◽  
Drain Current ◽  
Approximation Technique ◽  
Device Structure ◽  
Short Channel ◽  
Lateral Direction ◽  
Tunnel Fet ◽  
Surrounding Gate ◽  
Channel Effects ◽  
20 Nm

Analytical modelling for a tri material cylindrical gate tunnel FET is developed in this paper. Poisson equation and parabolic approximation technique are employed to develop the analytical model of the proposed device. Inorder to eliminate the influence of short channel effects and the leakage current, a surrounding gate with three different work function materials is used. Stacked dielectric or hetero-dielectric is used to improve the ON current of device. Performance of the device has been analyzed with different gate material lengths such as 10 nm, 15 nm and 20 nm. The developed 2-D mathematical model is used to obtain results like drain current, surface potential and electrical field in the vertical and lateral direction. From the results, a reduction in the device limitations is inferred and the leakage current is also considerably reduced. It has been found from the presented results that the proposed device structure Tri Material Cylindrical Gate Tunnel FET (TM CG TFET) provides the improved ON state current (10-3A/µm) and reduced OFF state current (10-14A/µm). The accuracy of the results and characteristics of the device are evaluated using TCAD simulations.

scholarly journals Triple Metal Surrounding Gate Junctionless Tunnel FET based 6T SRAM Design For Low Leakage Memory System

2021 ◽  
Author(s):  
G. LAKSHMI PRIYA ◽  
M. VENKATESH ◽  
N.B. BALAMURUGAN ◽  
T.S. ARUN SAMUEL
Keyword(s):  
Analytical Model ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Memory Systems ◽  
Low Leakage ◽  
Tunnel Fet ◽  
High K ◽  
Sram Design ◽  
Surrounding Gate ◽  
Hot Carrier Effects

Abstract The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET)based 6T SRAM structure is demonstrated by employing Germanium (Ge)and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D-TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model.

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