Modelling and Simulation of Hetero-Dielectric Surrounding Gate TFET

2020 ◽  
Vol 62 ◽  
pp. 47-58
Author(s):  
I. Vivek Anand ◽  
T.S. Arun Samuel ◽  
Palanichamy Vimala ◽  
A. Shenbagavalli
Keyword(s):  
Leakage Current ◽  
Drain Current ◽  
Approximation Technique ◽  
Device Structure ◽  
Short Channel ◽  
Lateral Direction ◽  
Tunnel Fet ◽  
Surrounding Gate ◽  
Channel Effects ◽  
20 Nm

Analytical modelling for a tri material cylindrical gate tunnel FET is developed in this paper. Poisson equation and parabolic approximation technique are employed to develop the analytical model of the proposed device. Inorder to eliminate the influence of short channel effects and the leakage current, a surrounding gate with three different work function materials is used. Stacked dielectric or hetero-dielectric is used to improve the ON current of device. Performance of the device has been analyzed with different gate material lengths such as 10 nm, 15 nm and 20 nm. The developed 2-D mathematical model is used to obtain results like drain current, surface potential and electrical field in the vertical and lateral direction. From the results, a reduction in the device limitations is inferred and the leakage current is also considerably reduced. It has been found from the presented results that the proposed device structure Tri Material Cylindrical Gate Tunnel FET (TM CG TFET) provides the improved ON state current (10-3A/µm) and reduced OFF state current (10-14A/µm). The accuracy of the results and characteristics of the device are evaluated using TCAD simulations.

scholarly journals Analysis of Low Dimensional Nanoscaled Inversion-Mode InGaAs MOSFETs for Next-Generation Electrical and Photonic Applications

2015 ◽  
Vol 2015 ◽  
pp. 1-6
Author(s):  
C. H. Yu ◽  
X. Y. Chen ◽  
X. D. Luo ◽  
W. W. Xu ◽  
P. S. Liu
Keyword(s):  
Leakage Current ◽  
Drain Current ◽  
Gate Oxide ◽  
Channel Length ◽  
Next Generation ◽  
Short Channel ◽  
Channel Effects ◽  
Operating Limits ◽  
Low Dimensional ◽  
Interface Passivation

The electrical characteristics of In0.53Ga0.47As MOSFET grown with Si interface passivation layer (IPL) and highkgate oxide HfO2layer have been investigated in detail. The influences of Si IPL thickness, gate oxide HfO2thickness, the doping depth, and concentration of source and drain layer on output and transfer characteristics of the MOSFET at fixed gate or drain voltages have been individually simulated and analyzed. The determination of the above parameters is suggested based on their effect on maximum drain current, leakage current, saturated voltage, and so forth. It is found that the channel length decreases with the increase of the maximum drain current and leakage current simultaneously. Short channel effects start to appear when the channel length is less than 0.9 μm and experience sudden sharp increases which make device performance degrade and reach their operating limits when the channel length is further lessened down to 0.5 μm. The results demonstrate the usefulness of short channel simulations for designs and optimization of next-generation electrical and photonic devices.

scholarly journals Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors

2013 ◽  
Vol 8 (2) ◽  
pp. 116-124
Author(s):  
Renan D. Trevisoli ◽  
Rodrigo T. Doria ◽  
Michelly De Souza ◽  
Marcelo Antonio Pavanello
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
Short Channel Effects ◽  
Subthreshold Slope ◽  
Short Channel ◽  
Nanowire Transistors ◽  
Channel Effects ◽  
20 Nm ◽  
Analytical Expressions ◽  
Controlled Doping

Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.

scholarly journals The Effect of Doping on Different FET Structures: MOSFET, TFET and FinFET

2020 ◽  
Vol 9 (6) ◽  
pp. 972-979
Keyword(s):  
Drain Current ◽  
Channel Length ◽  
Short Channel Effects ◽  
Poor Control ◽  
Short Channel ◽  
Circuit Performance ◽  
The Past ◽  
Channel Effects ◽  
Circuit Density ◽  
Effect Of Doping

MOSFET have been scaled down over the past few years in order to give rise to high circuit density and increase the speed of circuit. But scaling of MOSFET leads to issues such as poor control gate over the current which depends on gate voltage. Many short channel effects (SCE) influence the circuit performance and leads to the indeterminist response of drain current. These effects can be decreased by gate excitation or by using multiple gates and by offering better control gate the device parameters. In Single gate MOSFET, gate electric field decreases but multigate MOSFET or FinFET provides better control over drain current. In this paper, different FET structures such as MOSFET, TFET and FINFET are designed at 22nm channel length and effect of doping had been evaluated and studied. To evaluate the performance donor concentration is kept constant and acceptor concentration is varied.

scholarly journals Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Satyam Shukla ◽  
Sandeep Singh Gill ◽  
Navneet Kaur ◽  
H. S. Jatana ◽  
Varun Nehru
Keyword(s):  
Process Parameters ◽  
Simulation Analysis ◽  
Oxide Thickness ◽  
Channel Length ◽  
Deep Submicron ◽  
Device Structure ◽  
Short Channel ◽  
20 Nm ◽  
The Impact ◽  
Fin Shape

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.

scholarly journals Impact of multiple channels on the Characteristics of Rectangular GAA MOSFET

2017 ◽  
Vol 7 (4) ◽  
pp. 1899
Author(s):  
Mohammed Khaouani ◽  
Ahlam Guen-Bouazza
Keyword(s):  
Single Channel ◽  
Numerical Study ◽  
Drain Current ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel One ◽  
A Value ◽  
Device Structures ◽  
Channel Effects ◽  
The Impact

<p>Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number<em> </em>on the device’s DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 10<sup>4</sup>, while our four channels GAA MOSFET showed a value of 10<sup>3</sup>. In addition, a low value of drain induced barrier lowering<em> (DIBL) of </em>60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm.</p>

Synthesis of Low-Voltage Logic Gates on Surrounding Gate SOI CMOS Nanotransistors

2021 ◽  
Vol 23 (2) ◽  
pp. 75-82
Author(s):  
Masalsky N.V. ◽  
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Logic Gates ◽  
Active Power ◽  
Short Channel Effects ◽  
Short Channel ◽  
Switching Delay ◽  
Surrounding Gate ◽  
Channel Effects ◽  
Soi Cmos

We discuss the issues of synthesis of low-voltage logic gates on cylindrical surrounding gate SOI CMOS nanotransistors in the supply voltage range up to 0.8 V. In this transistor architecture, it becomes possible to more effectively control the charge in its working area, primarily due to its design parameters. It is also characterized by effective suppression of short-channel effects and a low capacitance value. This leads to a decrease in the level of power dissipation in combination with a reduction in the occupied area. TCAD models of n- and p-types nanotransistors have been developed. The anomalous behavior of the dependence of the threshold voltage on the diameter of the working area is revealed, which is associated with the peculiarities of the manifestation of short-channel effects due to the capacitive interaction of the gate-channel regions and drain-source transitions at small gate lengths. They were used to select prototypes of transistors with optimal parameters for the synthesis of complex logic gates with low supply voltage. Using the mathematical core of the HSPICE program, the dynamic characteristics of the developed physical models of the inverter, the inverter chain, and the XOR2 are numerically investigated. At control voltages of 0.8 V and a frequency of 50 GHz, the inverter model predicts a maximum switching delay of 3.3 ps, a limit level of active power of 1.1 mkW, static 0.3 pW, the XOR2 predicts a maximum switching delay of 8.6 ps, a limit level of active power of 4.9 mkW, static 1.5 pW. The minimum of the product "delay * power" of the adder is at a supply voltage of 0.72 V. Its position does not depend on the set of input signals. At the same time, the maximum switching delay is 10.8 ps, the maximum active power level is 3.9 mkW. The totality of the obtained characteristics allows us to consider the analyzed transistor architecture for creating low-power electronic devices.

50nm Gate-Length Hydrogen Terminated Diamond Field Effect Transistors – Characterization and Inspection of Operation.

2011 ◽  
Vol 1282 ◽  
Author(s):  
David A. J. Moran ◽  
Donald A. MacLaren ◽  
Samuele Porro ◽  
Richard Hill ◽  
Helen McLelland ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Gate Length ◽  
Short Channel Effects ◽  
Short Channel ◽  
Transmission Electron ◽  
Channel Effects ◽  
Physical And Chemical ◽  
Electron Energy Loss

ABSTRACTHydrogen terminated diamond field effect transistors (FET) of 50nm gate length have been fabricated, their DC operation characterised and their physical and chemical structure inspected by Transmission Electron Microscopy (TEM) and Electron Energy Loss Spectroscopy (EELS). DC characterisation of devices demonstrated pinch-off of the source-drain current can be maintained by the 50nm gate under low bias conditions. At larger bias, off-state output conductance increases, demonstrating most likely the onset of short-channel effects at this reduced gate length.

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