Moment Matched Gaussian Kernel and Region Representative Likelihood for Performance Improvement of PMF-based TRN

2020 ◽  
Vol 18 (7) ◽  
pp. 1691-1704 ◽  
Author(s):  
Chang-Ky Sung ◽  
Sang Jeong Lee
Keyword(s):  
Performance Improvement ◽  
Gaussian Kernel

scholarly journals Reliable Time Propagation Algorithms for PMF and RBPMF

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 261
Author(s):  
Chang-Ky Sung ◽  
Sang Jeong Lee
Keyword(s):  
Performance Improvement ◽  
Nonlinear Models ◽  
Linear Interpolation ◽  
Statistical Characteristics ◽  
Gaussian Kernel ◽  
Process Noise ◽  
Computational Load ◽  
Kernel Length ◽  
Time Propagation ◽  
Grid Interval

This paper addresses the reliable time propagation algorithms for Point Mass Filter (PMF) and Rao–Blackwellized PMF (RBPMF) for the nonlinear estimaton problem. The conventional PMF and RBPMF process the probability diffusion for the time propagation with the direct sampled-values of the process noise. However, if the grid interval is not dense enough, it fails to represent the statistical characteristics of the noise accurately so the performance might deteriorate. To overcome that problem, we propose time propagation convolution algorithms adopting Moment Matched Gaussian Kernel (MMGK) on regular grids through mass linear interpolation. To extend the dimension of the MMGK that can accurately describe the noise moments up to the kernel length, we propose the extended MMGK based on the outer tensor product. The proposed time propagation algorithms using one common kernel through the mass linear interpolation not only improve the performance of the filter but also significantly reduce the computational load. The performance improvement and the computational load reduction of the proposed algorithms are verified through numerical simulations for various nonlinear models.

Helicopter main reduction planetary gear fault diagnosis method based on SVDD

2020 ◽  
Vol 64 (1-4) ◽  
pp. 137-145
Author(s):  
Yubin Xia ◽  
Dakai Liang ◽  
Guo Zheng ◽  
Jingling Wang ◽  
Jie Zeng
Keyword(s):  
Fault Diagnosis ◽  
Planetary Gear ◽  
Gaussian Kernel ◽  
Support Vector ◽  
Support Vector Data Description ◽  
Vector Data ◽  
Energy Characteristics ◽  
Gear Fault ◽  
Channel Information ◽  
Diagnosis Method

Aiming at the irregularity of the fault characteristics of the helicopter main reducer planetary gear, a fault diagnosis method based on support vector data description (SVDD) is proposed. The working condition of the helicopter is complex and changeable, and the fault characteristics of the planetary gear also show irregularity with the change of working conditions. It is impossible to diagnose the fault by the regularity of a single fault feature; so a method of SVDD based on Gaussian kernel function is used. By connecting the energy characteristics and fault characteristics of the helicopter main reducer running state signal and performing vector quantization, the planetary gear of the helicopter main reducer is characterized, and simultaneously couple the multi-channel information, which can accurately characterize the operational state of the planetary gear’s state.

Peningkatan kinerja guru dalam pembelajaran di kelas melalui supervisi edukatif Kolaboratif secara periodik MIS Lawe kongker Tahun pelajaran 2019/2020

2020 ◽  
Vol 1 (3) ◽  
pp. 316-324
Author(s):  
Syukrani Kadir
Keyword(s):  
Student Learning ◽  
Performance Improvement ◽  
Teacher Performance ◽  
Learning Cycle ◽  
Learning Achievement ◽  
Educational Supervision ◽  
Average Action ◽  
Learning Plans

periodically in preparing learning plans, implementing learning, assessing learning achievement, carrying out follow-up assessments of student learning achievement that can improve teacher performance. This performance improvement is through periodic collaborative educational supervision. Based on the results of educational supervision in cycle I and cycle II, teacher performance increased, namely in cycle I, teacher performance in preparing learning plans in cycle I reached 71.98%, while cycle II was 92.44%. Teacher performance in implementing learning cycle I reached 72.44% while cycle II reached 93.81%. Teacher performance in assessing learning achievement in cycle Im reached 81.30% while cycle II was 90.56%. Teacher performance in carrying out follow-up assessments of student learning achievement in the first cycle reached 59.76% while the second cycle was 83.00%. Thus, the average action cycle II was above 75.00%. Based on the results of this study, it can be concluded that the teacher's performance has increased in preparing learning plans, implementing learning, assessing learning achievement, carrying out follow-up assessments of student learning achievement.

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko
Keyword(s):  
Performance Improvement ◽  
Experimental Studies ◽  
Production Costs ◽  
Floating Point ◽  
Computing Device ◽  
Quartus Ii ◽  
Functional Blocks ◽  
Mental Testing ◽  
Processor Cores ◽  
Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

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