Characterization of large area devices by an improved constant capacitance voltage transient technique

Solar Cells ◽  
1988 ◽  
Vol 24 (3-4) ◽  
pp. 363-369
Author(s):  
Jeng-Jye Shiau ◽  
Alen L. Fahrenbruch ◽  
Richard H. Bube
1994 ◽  
Vol 9 (9) ◽  
pp. 1637-1648 ◽  
Author(s):  
S Duenas ◽  
E Castan ◽  
L Enriquez ◽  
J Barbolla ◽  
J Montserrat ◽  
...  

2012 ◽  
Vol 717-720 ◽  
pp. 1187-1189
Author(s):  
Ruby N. Ghosh ◽  
Reza Loloee

SiC based capacitive devices have the potential to operate in high temperature, chemically corrosive environments provided that the electrical integrity of the gate oxide and metallization can be maintained in these environments. We report on the performance of large area, up to 8 x 10-3 cm2, field-effect capacitive sensors fabricated on both the 4H and 6H polytypes at 600°C. Large area capacitors improve the signal/noise (S/N) ratio which is proportional to the slope of the capacitance-voltage characteristic. At 600 °C we obtain a S/N ~ 20. The device response is independent of polytype, either 4H or 6H-SiC. These results demonstrate the reliability of our field-effect structure, operating as a simple potentiometer at high temperature.


1989 ◽  
Vol 65 (7) ◽  
pp. 2734-2738 ◽  
Author(s):  
M. B. Chang ◽  
H. Tomokage ◽  
J. J. Shiau ◽  
R. H. Bube ◽  
J. C. Bravman

Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.


Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.


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