Short minority carrier response time in HfO2 /Ge metal-insulator-semiconductor capacitors

2005 ◽  
Vol 80 ◽  
pp. 34-37 ◽  
Author(s):  
A. Dimoulas ◽  
G. Vellianitis ◽  
G. Mavrou ◽  
E.K. Evangelou ◽  
K. Argyropoulos ◽  
...  
Keyword(s):  
Response Time ◽  
Minority Carrier ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor

Impact of the Gate Material on the Deep Levels in a-Si:H/c-Si Metal-Insulator-Semiconductor Capacitors

2015 ◽  
Vol 242 ◽  
pp. 61-66
Author(s):  
Eddy Simoen ◽  
Valentina Ferro ◽  
Barry O’Sullivan
Keyword(s):  
Minority Carrier ◽  
Crystalline Silicon ◽  
Deep Level ◽  
Silicon Layer ◽  
Si Substrate ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Transient Spectroscopy ◽  
P Type ◽  
Mis Capacitors

Deep Level Transient Spectroscopy (DLTS) has been applied to Metal-Insulator-Semiconductor (MIS) capacitors, consisting of a p+ or n+ a-Si:H gate on an intrinsic i-a-Si:H passivation layer deposited on crystalline silicon n-or p-type substrates. It is shown that the type of gate has a pronounced impact on the obtained spectra, whereby both the kind of defects (dangling bonds at the a-Si:H/(100) c-Si interface (Pb0 defects) or in the amorphous silicon layer (D defects) and their relative importance (peak amplitude) may be varied. The highest trap densities have been found for the p+ a-Si:H gate capacitors on an n-type Si substrate. In addition, the spectra may exhibit unexpected negative peaks, suggesting minority carrier capture. These features are tentatively associated with interface states at the p+ or n+ a-Si:H/i-a-Si:H interface. Their absence in Al-gate capacitors is in support of this hypothesis.

Importance of minority carrier response in accurate characterization of Ge metal-insulator-semiconductor interface traps

2009 ◽  
Vol 106 (4) ◽  
pp. 044506 ◽  
Author(s):  
Noriyuki Taoka ◽  
Toyoji Yamamoto ◽  
Masatomi Harada ◽  
Yoshimi Yamashita ◽  
Naoharu Sugiyama ◽  
...  
Keyword(s):  
Minority Carrier ◽  
Interface Traps ◽  
Semiconductor Interface ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor

scholarly journals Prototype of Nitro Compound Vapor and Trace Detector Based on a Capacitive MIS Sensor

Sensors ◽  
2020 ◽  
Vol 20 (5) ◽  
pp. 1514 ◽  
Author(s):  
Nikolay Samotaev ◽  
Artur Litvinov ◽  
Maya Etrekova ◽  
Konstantin Oblov ◽  
Dmitrii Filipchuk ◽  
...  
Keyword(s):  
Detection Limit ◽  
Response Time ◽  
Gas Sensor ◽  
Nitro Compound ◽  
Structure Type ◽  
Mis Structure ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Pyrolysis Method ◽  
Prototype Detector

A prototype of a nitro compound vapor and trace detector, which uses the pyrolysis method and a capacitive gas sensor based on the metal–insulator–semiconductor (MIS) structure type Pd–SiO2–Si, was developed and manufactured. It was experimentally established that the detection limit of trinitrotoluene trace for the detector prototype is 1 × 10−9 g, which corresponds to concentration from 10−11 g/cm3 to 10−12 g/cm3. The prototype had a response time of no more than 30 s. The possibility of further improving the characteristics of the prototype detector by reducing the overall dimensions and increasing the sensitivity of the MIS sensors is shown.

Co-planar two-dimensional Metal-Insulator-Semiconductor Capacitor: Numerical study of the device electrostatics.

2017 ◽  
Author(s):  
Varun Bheemireddy
Keyword(s):  
Space Charge ◽  
High Performance ◽  
Numerical Study ◽  
2D Materials ◽  
Space Charge Density ◽  
Two Dimensional ◽  
Short Channel ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
New Family

The two-dimensional(2D) materials are highly promising candidates to realise elegant and e cient transistor. In the present letter, we conjecture a novel co-planar metal-insulator-semiconductor(MIS) device(capacitor) completely based on lateral 2D materials architecture and perform numerical study of the capacitor with a particular emphasis on its di erences with the conventional 3D MIS electrostatics. The space-charge density features a long charge-tail extending into the bulk of the semiconductor as opposed to the rapid decay in 3D capacitor. Equivalently, total space-charge and semiconductor capacitance densities are atleast an order of magnitude more in 2D semiconductor. In contrast to the bulk capacitor, expansion of maximum depletion width in 2D semiconductor is observed with increasing doping concentration due to lower electrostatic screening. The heuristic approach of performance analysis(2D vs 3D) for digital-logic transistor suggest higher ON-OFF current ratio in the long-channel limit even without third dimension and considerable room to maximise the performance of short-channel transistor. The present results could potentially trigger the exploration of new family of co-planar at transistors that could play a signi significant role in the future low-power and/or high performance electronics.<br>

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