Thermal transient characteristics of die attach in high power LED PKG

2008 ◽  
Vol 48 (3) ◽  
pp. 445-454 ◽  
Author(s):  
Hyun-Ho Kim ◽  
Sang-Hyun Choi ◽  
Sang-Hyun Shin ◽  
Young-Ki Lee ◽  
Seok-Moon Choi ◽  
...  
2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001585-001605 ◽  
Author(s):  
Paul Panaccione ◽  
Tao Wang ◽  
Guo-Quan Lu ◽  
Xu Chen ◽  
Susan Luo

Heat removal in packaged high-power light-emitting diode (LED) chips is critical to device performance and reliability. Thermal performance of LEDs is important in that lowered junction temperatures extend the LED's lifetime at a given photometric flux (brightness). Optionally, lower thermal resistance can enable increased brightness operation without exceeding the maximum allowable Tj for a given lifetime. A significant portion of the junction-to-case thermal resistance comes from the joint between chip and substrate, or the die-attach layer. In this study, we evaluated three different types of leading die-attach materials; silver epoxy, lead-free solder, and an emerging nanosilver paste. Each of the three was processed via their respective physical and chemical mechanisms: epoxy curing by cross-linking of polymer molecules; intermetalic soldering by reflow and solidification; and nanosilver sintering by solid-state atomic diffusion. High-power LED chips with a chip area of 3.9 mm2 were attached by the three types of materials onto metalized aluminum nitride substrates, wire-bonded, and then tested in an electro-optical setup. The junction-to-heatsink thermal resistance of each LED assembly was determined by the wavelength shift methodology, described in detail in this paper. We found that the average thermal resistance in the chips attached by the nanosilver paste was the lowest, and it is the highest from the chips attached by the silver epoxy: the difference between the two was about 0.7°C/W, while the difference between the sintered and soldered was about 0.3°C/W. The lower thermal resistance in the sintered joints is expected to significantly improve the photometric flux from the device. Simple calculations, excluding high current efficiency droop, predict that the brightness improvement could be as high as 50% for the 3.9 mm2 chip. The samples will be functionally tested at high current, in both steady-state and pulsed operation, to determine brightness improvements, including the impact of droop. Nanosilver die-attach on a range of chip sizes up to 12 mm2 are also considered and discussed.


2016 ◽  
Vol 37 (9) ◽  
pp. 1159-1165
Author(s):  
陈佳 CHEN Jia ◽  
李欣 LI Xin ◽  
孔亚飞 KONG Ya-fei ◽  
梅云辉 MEI Yun-hui ◽  
陆国权 LU Guo-quan

2010 ◽  
Vol 7 (3) ◽  
pp. 164-168 ◽  
Author(s):  
Paul Panaccione ◽  
Tao Wang ◽  
Xu Chen ◽  
Susan Luo ◽  
Guo-Quan Lu

Heat removal in packaged high-power light-emitting diode (LED) chips is critical to device performance and reliability. Thermal performance of LEDs is important in that lowered junction temperatures extend the LED's lifetime at a given pho-tometric flux (brightness). Optionally, lower thermal resistance can enable increased brightness operation without exceeding the maximum allowable Tj for a given lifetime. A significant portion of the junction-to-case thermal resistance comes from the joint between chip and substrate, or the die-attach layer. In this study, we evaluated three different types of leading die-attach materials; silver epoxy, lead-free solder, and an emerging nanosilver paste. Each of the three was processed via their respective physical and chemical mechanisms: epoxy curing by cross-linking of polymer molecules; intermetalic soldering by reflow and solidification; and nanosilver sintering by solid-state atomic diffusion. High-power LED chips with a range of chip areas from 3.9 mm2 to 9.0 mm2 were attached by the three types of materials onto metalized aluminum nitride substrates, wire-bonded, and then tested in an electro-optical setup. The junction-to-heatsink thermal resistance of each LED assembly was determined by the wavelength shift methodology. We found that the average thermal resistance in the chips attached by the nanosilver paste was the lowest, and it was highest from the chips attached by the silver epoxy. For the 3.9 mm2 die, the difference was about 0.6°C/W, while the difference between the sintered and soldered was about 0.3°C/W. The lower thermal resistance in the sintered joints is expected to significantly improve the photometric flux from the device. Simple calculations, excluding high current efficiency droop, predict that the brightness improvement could be as high as 50% for the 3.9 mm2 chip. The samples will be functionally tested at high current, in both steady-state and pulsed operation, to determine brightness improvements, including the impact of droop. Nanosilver die-attach on a range of chip sizes up to 12 mm2 are also considered and discussed.


2015 ◽  
Vol 62 (11) ◽  
pp. 3715-3721 ◽  
Author(s):  
Wei Lai ◽  
Xianming Liu ◽  
Weimin Chen ◽  
Xiaohua Lei ◽  
Xueying Cao

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Piaopiao He ◽  
Jinlong Zhang ◽  
Jianhua Zhang ◽  
Luqiao Yin

The reliability of high-power light-emitting-diode (LED) devices strongly depends on the die-attach quality because voids may increase junction temperature and total thermal resistance of LED devices. Die-attach material has a key role in the thermal management of high-power LED package by providing low-contact thermal resistance. Thermal and mechanical analyses were carried out by experiments and thermal simulation. The quantitative analysis results show that thermal resistance of die-attach layer (thermal resistance caused by die-attach material and voids in die-attach layer) plays an important role in total thermal resistance of high-power LED packaging according to the differential structure function of thermal transient characteristics. The increase of void fraction in die-attach layer causes the increases of thermal resistance of die-attach layer; the thermal resistance increased by 1.95 K/W when the void fraction increased to 62.45%. The voids also make an obvious influence on thermal stress and thermal strain of chip; the biggest thermal stress of chip was as high as 847.1 MPa compared to the 565.2 MPa when the void fraction increases from being void-free to 30% in the die-attach layer.


2013 ◽  
Vol 44 (11) ◽  
pp. 1005-1010 ◽  
Author(s):  
Stefan Müller ◽  
Thomas Zahner ◽  
Frank Singer ◽  
Gabriele Schrag ◽  
Gerhard Wachutka

2016 ◽  
Vol 853 ◽  
pp. 389-393 ◽  
Author(s):  
Jia Chen ◽  
Xin Li ◽  
Ya Fei Kong

Along with the increasing demand of high power LED (>1W), multi-chip modules have made great progress to an inevitable trend. Thus, large packaging area is needed to dissipate heat efficiently. In other words, only when we find appropriate packaging materials to control the junction temperature well, can we achieve high-power LED devices in smaller packaging area. Obviously, a die-attach layer as the first-level packaging has a most significant impact on the thermal performance of a power module. So we introduce a novel die-attach material, nanosilver paste, which can be used for connecting multi-chips on the substrate because of its higher melting temperature and better thermal/electrical conductivity than conventional solders and adhesive films. What is more important, because of their ability to emit high brightness, LED packages are being exploited for other systems or fields, and in most cases are exposed to harsher environments. Therefore, the performance and stability of LED packages will be the key to assuring the reliable function of systems. So, in this paper, the optical and electrical properties of the LED device operating under various ambient temperatures from 27 to 120°C were determined. The test results showed that nanosilver paste was a very promising die-attach material in high power multi-chip modules packaging.


2010 ◽  
Author(s):  
Chien-Ping Wang ◽  
Tzung-Te Chen ◽  
Shih-Chun Yang ◽  
Han-Kuei Fu ◽  
An-Tse Lee ◽  
...  

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