Study of Thermal Stress Fluctuations at the Die-Attach Solder Interface Using the Finite Element Method

Solder joints in electronic packages are frequently exposed to thermal cycling in both real-life applications and accelerated thermal cycling tests. Cyclic temperature leads the solder joints to be subjected to cyclic mechanical loading and often accelerates the cracking failure of the solder joints. The cause of stress generated in thermal cycling is usually attributed to the coefficients of thermal expansion (CTE) mismatch of the assembly materials. In a die-attach structure consisting of multiple layers of materials, the effect of their CTE mismatch on the thermal stress at a critical location can be very complex. In this study, we investigated the influence of different materials in a die-attach structure on the stress at the chip–solder interface with the finite element method. The die-attach structure included a SiC chip, a SAC solder layer and a DBC substrate. Three models covering different modeling scopes (i.e., model I, chip–solder layer; model II, chip–solder layer and copper layer; and model III, chip–solder layer and DBC substrate) were developed. The 25–150 °C cyclic temperature loading was applied to the die-attach structure, and the change of stress at the chip–solder interface was calculated. The results of model I showed that the chip–solder CTE mismatch, as the only stress source, led to a periodic and monotonic stress change in the temperature cycling. Compared to the stress curve of model I, an extra stress recovery peak appeared in both model II and model III during the ramp-up of temperature. It was demonstrated that the CTE mismatch between the solder and copper layer (or DBC substrate) not only affected the maximum stress at the chip–solder interface, but also caused the stress recovery peak. Thus, the combined effect of assembly materials in the die-attach structure should be considered when exploring the joint thermal stresses.

Degradation mechanisms analysis for SiC power MOSFETs under repetitive power cycling stress

In this work, investigation on the degradation behavior of the 1.2-kV/52-A silicon carbide (SiC) power MOSFETs subjected to repetitive slow power cycling stress have been performed. Electric characteristics have been characterized periodically over the stress and the respective degradation mechanisms also have been analysed. A comprehensive degradation analysis is further conducted after the aging test by virtue of the X-ray inspection system, Scanning Acoustic Microscope (SAM), Scanning Electron Microscope (SEM) and emission microscope (EMMI), etc. Experimental results reveal that both the degradation of gate oxide on chip-level and the degradation of the bond wire and solder layer on package-level have emerged over the cyclic stress. Specifically, growths of threshold voltage (Vth) and gate leakage current (Igss) are thought to be relevant with the degradation of gate oxide by SiC/SiO2 interface states trapping/de-trapping electron on chip-level, while the appearances of the fatigue of bond wire and the delamination of solder layer imply the degradation on package-level. This work may provide some practical guidelines for the assessments towards the reliability of SiC power MOSFETs in power conversion system.