Constant voltage stress characterization of nFinFET transistor during total ionizing dose experiment

2018 ◽  
Vol 88-90 ◽  
pp. 969-973
Author(s):  
B. Li ◽  
Y. Huang ◽  
J. Wu ◽  
Y. Huang ◽  
B. Li ◽  
...  
2014 ◽  
Vol 14 (5) ◽  
pp. 543-548 ◽  
Author(s):  
Ho-Young Kwak ◽  
Sung-Kyu Kwon ◽  
Hyuk-Min Kwon ◽  
Seung-Yong Sung ◽  
Su Lim ◽  
...  

2012 ◽  
Vol 52 (9-10) ◽  
pp. 1895-1900 ◽  
Author(s):  
Philippe Chiquet ◽  
Pascal Masson ◽  
Romain Laffont ◽  
Gilles Micolau ◽  
Jérémy Postel-Pellerin ◽  
...  

2007 ◽  
Vol 46 (4B) ◽  
pp. 1879-1884 ◽  
Author(s):  
Toshifumi Sago ◽  
Akiyoshi Seko ◽  
Mitsuo Sakashita ◽  
Akira Sakai ◽  
Masaki Ogawa ◽  
...  

2008 ◽  
Vol 55 (6) ◽  
pp. 1359-1365 ◽  
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Kenichi Takeda ◽  
Renichi Yamada ◽  
Toshinori Imai ◽  
Tsuyoshi Fujiwara ◽  
Takashi Hashimoto ◽  
...  

2010 ◽  
Vol 1252 ◽  
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Sahar Sahhaf ◽  
Robin Degraeve ◽  
Mohammed Zahid ◽  
Guido Groeseneken

AbstractIn this work, the effect of elevated temperature on the generated defects with constant voltage stress (CVS) in SiO2 and SiO2/HfSiO stacks is investigated. Applying Trap Spectroscopy by Charge Injection and Sensing (TSCIS) to 6.5 nm SiO2 layers, different kinds of generated traps are profiled at low and high temperature. Also the Stress-Induced Leakage Current (SILC) spectrum of high-k dielectric stack is different at elevated temperature indicating that degradation and breakdown at high temperature is not equivalent to that at low temperature and therefore, extrapolation of data from high to low T or vice versa is challenging.


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