Influence of Germanium source on dopingless tunnel-FET for improved analog/RF performance

2017 ◽  
Vol 101 ◽  
pp. 244-252 ◽  
Author(s):  
Kanchan Cecil ◽  
Jawar Singh
Keyword(s):  
2021 ◽  
Author(s):  
Ritam Dutta ◽  
Nitai Paitya ◽  
Manisha Rahaman ◽  
Ankita Guha ◽  
Priya Kumari
Keyword(s):  

2016 ◽  
Vol 91 ◽  
pp. 319-330 ◽  
Author(s):  
Sudhansu Mohan Biswal ◽  
Biswajit Baral ◽  
Debashis De ◽  
Angsuman Sarkar

Author(s):  
Sidhartha Dash ◽  
Guru Prasad Mishra

Introduction: Here, we have presented an n-channel cylindrical gate tunnel FET with drain underlap engineering (CGT-DU) and the simulation process is carried out using 3-D device simulator from Synopsys. Methods: The analog and radio frequency (RF) performance of the device has been studied extensively in terms of electric field, energy band analysis, drain current, gain bandwidth product, unity gain cut‐off frequency, transconductance frequency product, and maximum oscillation frequency for different values of drain underlap length. Results: The increase in underlap length in CGT paves way for substantial reduction in ambipolar current without degrading the ON-state current. The proposed device exhibits lower lateral electric field, larger tunneling length and lower gate to drain capacitance at the drain end with higher underlap length. Conclusion: CGT-DU exhibits superior ambipolar and RF performance without degrading ON-state current and threshold voltage.


Micromachines ◽  
2020 ◽  
Vol 11 (11) ◽  
pp. 960
Author(s):  
Jun Li ◽  
Ying Liu ◽  
Su-fen Wei ◽  
Chan Shan

In this paper, we present an in-built N+ pocket electrically doped tunnel FET (ED-TFET) based on the polarity bias concept that enhances the DC and analog/RF performance. The proposed device begins with a MOSFET like structure (n-p-n) with a control gate (CG) and a polarity gate (PG). The PG is biased at −0.7 V to induce a P+ region at the source side, leaving an N+ pocket between the source and the channel. This technique yields an N+ pocket that is realized in the in-built architecture and removes the need for additional chemical doping. Calibrated 2-D simulations have demonstrated that the introduction of the N+ pocket yields a higher ION and a steeper average subthreshold swing when compared to conventional ED-TFET. Further, a local minimum on the conduction band edge (EC) curve at the tunneling junction is observed, leading to a dramatic reduction in the tunneling width. As a result, the in-built N+ pocket ED-TFET significantly improves the DC and analog/RF figure-of-merits and, hence, can serve as a better candidate for low-power applications.


2021 ◽  
Author(s):  
PRABHAT SINGH ◽  
DHARMENDRA SINGH YADAV

Abstract In this manuscript, a novel physically doped single gate F-shaped tunnel FET is simulated and optimized. The designed configuration is well optimized and analyzed for different source thickness, source length, drain length with different lateral tunneling lengths between the source edge and gate dielectric. Also, we optimized some stand-points like threshold voltage, ION to IOFF current ratio, ambipolar conduction range, subthreshold swing and various capacitance to rectify the analog/RF performance of single gate F-shaped TFET. Regarding this, we concurrently optimize the lateral tunneling length between source and gate with optimization of source thickness. The variation in lateral tunneling length, the potential and strength of electric field at fixed Vgs voltage is varied which leads to effective change in the ON-current, average sub-threshold swing, and turn ON-voltage. Another side, as well as the source thickness vary, the electric field variation takes place near the edge of source, which leads to variation in the ON-current and ON-voltage. The performance parameters of single gate F-TFET is compared with single gate L-TFET, which is the incentive of this submitted work. The optimized single gate F-TFET have 0.30 V turn ON-voltage with 7.4 mV/decade average sub-threshold swing and high Ion/Ioff ratio approx 1013. Besides, a significant reduction in parasitic capacitance is beneficial to enhanced RF performance with better controllability on channel.


2020 ◽  
Vol 67 (4) ◽  
pp. 1873-1879 ◽  
Author(s):  
Tripuresh Joshi ◽  
Yashvir Singh ◽  
Balraj Singh

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