Impact of Different III-V material used in Source of Dual Gate Tri-Metal n-type Tunnel FET for Improved RF Performance

2021 ◽  
Author(s):  
Ritam Dutta ◽  
Nitai Paitya ◽  
Manisha Rahaman ◽  
Ankita Guha ◽  
Priya Kumari
Keyword(s):  
Tunnel Fet ◽  
Dual Gate ◽  
Rf Performance

scholarly journals A SiGe-Source Doping-Less Double-Gate Tunnel FET: Design and Analysis Based on Charge Plasma Technique with Enhanced Performance

2021 ◽  
Author(s):  
Varun Mishra ◽  
Yogesh Kumar Verma ◽  
Santosh Kumar Gupta ◽  
Vikas Rathi
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Source Material ◽  
Double Gate ◽  
Charge Plasma ◽  
Plasma Technique ◽  
Tunnel Fet ◽  
Distortion Analysis ◽  
Dual Gate ◽  
Rf Performance

Abstract In this article, a distinctive charge plasma (CP) technique is employed to design two doping-less dual gate tunnel field effect transistors (DL-DG-TFETs) with Si0.5Ge0.5 and Si as source material. The CP methodology resolves the issues of random doping fluctuation and doping activation. The analog and RF performance has been investigated for both the proposed devices i.e. Si0.5Ge0.5 source DL-DG-TFET and Si-source DL-DG-TFET in terms of drive current, transconductance, cut-off frequency. In addition, the linearity and distortion analysis has been carried out for both the proposed devices with respect to higher order transconductance (gm2 and gm3), VIP2, IMD3, and HD2. The Si0.5Ge0.5 source DL-DG-TFET has better performance characteristics and reliability in compare to Si-source DL-DG-TFET owing to low energy bandgap material and higher mobility. The switching ratio obtained for Si0.5Ge0.5 source DL-DG-TFET is order of 5×1014 that makes it a suitable contender for low power applications.

Study of effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire Tunnel FET

2016 ◽  
Vol 91 ◽  
pp. 319-330 ◽  
Author(s):  
Sudhansu Mohan Biswal ◽  
Biswajit Baral ◽  
Debashis De ◽  
Angsuman Sarkar
Keyword(s):  
Gate Length ◽  
Tunnel Fet ◽  
Rf Performance

Impact of Drain Underlap Length Variation on the DC and RF Performance of Cylindrical Gate Tunnel FET

2020 ◽  
Vol 10 ◽  
Author(s):  
Sidhartha Dash ◽  
Guru Prasad Mishra
Keyword(s):  
Electric Field ◽  
Substantial Reduction ◽  
Drain Current ◽  
Current Gain ◽  
Field Energy ◽  
Length Variation ◽  
Gain Bandwidth ◽  
Tunnel Fet ◽  
Unity Gain ◽  
Rf Performance

Introduction: Here, we have presented an n-channel cylindrical gate tunnel FET with drain underlap engineering (CGT-DU) and the simulation process is carried out using 3-D device simulator from Synopsys. Methods: The analog and radio frequency (RF) performance of the device has been studied extensively in terms of electric field, energy band analysis, drain current, gain bandwidth product, unity gain cut‐off frequency, transconductance frequency product, and maximum oscillation frequency for different values of drain underlap length. Results: The increase in underlap length in CGT paves way for substantial reduction in ambipolar current without degrading the ON-state current. The proposed device exhibits lower lateral electric field, larger tunneling length and lower gate to drain capacitance at the drain end with higher underlap length. Conclusion: CGT-DU exhibits superior ambipolar and RF performance without degrading ON-state current and threshold voltage.

An Accurate Drain Current Model for Symmetric Dual Gate Tunnel FET Using Effective Tunneling Length

2018 ◽  
Vol 9 (1) ◽  
pp. 85-91 ◽  
Author(s):  
Sasmita Sahoo ◽  
Sidhartha Dash ◽  
Guru P. Mishra
Keyword(s):  
Performance Indicators ◽  
Analytical Modeling ◽  
Present Model ◽  
Current Model ◽  
Practical Importance ◽  
Drain Current ◽  
Subthreshold Slope ◽  
Tunnel Fet ◽  
Dual Gate ◽  
Tcad Sentaurus

Introduction: Here we propose an accurate drain current model for a Symmetric Dual Gate Tunnel FET (SDG-TFET) using effective tunneling length and generation rate of carrier over tunneling junction area. Analytical Modeling: The surface potential of the model is obtained by solving 2-dimensional Poisson’s equation and further extends to determine the magnitude of initial tunneling length and final tunneling length. The different DC performance indicators like drain current (ID), threshold voltage (Vth), transconductance (gm) and Subthreshold Slope (SS) for the present model are extensively investigated and the results are compared with that of Single Gate Tunnel FET (SGTFET). Conclusion: The practical importance of this model relies on its accuracy and improved electrostatic performance over SG-TFET. The analytical model results are validated using TCAD Sentaurus (Synopsys) device simulator.

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