Gate-on-drain overlapped L-shaped channel Tunnel FET as label-free biosensor

In this manuscript gate-on-drain L-shaped channel Tunnel FET is proposed to detect various biomolecules through label-free bio-sensing detection technique. Biomolecules can be detected in the proposed structure through modulating ambipolar current between channel and drain by overlapping gate on drain thus creating a cavity. Trapped biomolecules within cavity gets immobilized. Immobilized biomolecules change the drain to channel tunneling width, thus changing the ambiploar leakage current. Drain doping and cavity length was fine-tuned to achieve better sensitivity in terms of ambipolar current and ambipolar knee voltage shift with and without presence of biomolecules. A maximum sensitivity of 3.8×107 is achieved for drain doping of 5×1019 donors/cm3 and cavity length of 60nm. A high value of sensitivity is achieved for each biomolecules when drain doping ranged from 1019 donors/cm3 to 5×1019 donors/cm3 and cavity length ranged between 40nm to 50nm. Effect of differently charged biomolecules on sensitivity has also be structured.

In-Built N+ Pocket Electrically Doped Tunnel FET With Improved DC and Analog/RF Performance

In this paper, we present an in-built N+ pocket electrically doped tunnel FET (ED-TFET) based on the polarity bias concept that enhances the DC and analog/RF performance. The proposed device begins with a MOSFET like structure (n-p-n) with a control gate (CG) and a polarity gate (PG). The PG is biased at −0.7 V to induce a P+ region at the source side, leaving an N+ pocket between the source and the channel. This technique yields an N+ pocket that is realized in the in-built architecture and removes the need for additional chemical doping. Calibrated 2-D simulations have demonstrated that the introduction of the N+ pocket yields a higher ION and a steeper average subthreshold swing when compared to conventional ED-TFET. Further, a local minimum on the conduction band edge (EC) curve at the tunneling junction is observed, leading to a dramatic reduction in the tunneling width. As a result, the in-built N+ pocket ED-TFET significantly improves the DC and analog/RF figure-of-merits and, hence, can serve as a better candidate for low-power applications.

Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors

In this paper, a two dimensional analytical model of the threshold voltage for HGD TFET structure has been proposed. We have also presented the analytical models for the tunneling width and the channel potential. The potential model is used to develop the physics based model of threshold voltage by exploring the transition between linear to exponential dependence of drain current on the gate bias. The proposed model depends on the drain voltage, gate dielectric near the source and drain, silicon film thickness, work function of gate metal and oxide thickness. The accuracy of the proposed model is verified by simulation results of 2-D ATLAS simulator. Due to the reduction of the equivalent oxide thickness, the coupling between the gate and the channel junction enhances which results in lower threshold voltage. Tunneling width becomes narrower at a given gate voltage for the optimum channel concentration of 1016 /cm3. The higher concentration in the source (Ns) causes a steep bending in the conduction and valence bands compared to the lower concentration which results in smaller tunneling width at the source-channel interface.

Enhanced Tunneling through sub 30 Angstroms Thick Gallium Nitride Cap Layers on Silicon Carbide for Low Contact Resistance

We present numerical calculations of tunneling through ultra thin wurtzite Gallium Nitride cap layers on p-doped wurtzite silicon carbide . We demonstrate the predominance of tunneling of the split-off holes to the total carrier flux, with the contribution of the heavy and the light holes damped by the large potential barrier. We calculate the contributions of spontaneous and piezoelectric polarizations to the tunneling profile seen by the holes. Two orders of magnitude enhancement is seen in the transmission probabilities for a 10 angstroms thick Gallium Nitride cap layer for holes very close to the valence band edge, compared to a barrier without any gallium nitride cap. The contact resistances are also calculated for the Gallium Nitride tunneling caps and more than two orders of magnitude lowering is seen with the ultra-thin caps. Larger cap widths induce hole accumulation layers, but the advantages of hole accumulation are offset by the higher effective tunneling width. Our calculations are relevant to nanostructures and nanodevices involving heterojunctions between gallium nitride and silicon carbide and provide the basis for low contact resistances with as-deposited metals. While our calculations focus on the regime of very high barriers to the metal of the order of 1.5 - 2 electron volts, where the method of ultra-thin caps is most useful, similar conclusions also hold for lower barrier heights.