GaAs0.5Sb0.5/ In0.53Ga0.47As heterojunction dopingless charge plasma-based tunnel FET for analog/digital performance improvement

Superlattices and Microstructures ◽

10.1016/j.spmi.2020.106522 ◽

2020 ◽

Vol 142 ◽

pp. 106522

Author(s):

Amit Bhattacharyya ◽

Manash Chanda ◽

Debashis De

Keyword(s):

Performance Improvement ◽

Charge Plasma ◽

Digital Performance ◽

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Performance Improvement in Nanoscale Ge–GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate

Journal of Low Power Electronics ◽

10.1166/jolpe.2014.1348 ◽

2014 ◽

Vol 10 (3) ◽

pp. 354-360 ◽

Author(s):

Bahniman Ghosh ◽

Shibir Basak ◽

Pranav Kumar Asthana

Keyword(s):

Performance Improvement ◽

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Gate misalignment effects on analog/RF performance of charge plasma-based doping-less tunnel FET

Applied Physics A ◽

10.1007/s00339-017-1029-8 ◽

2017 ◽

Vol 123 (6) ◽

Author(s):

Sunny Anand ◽

R. K. Sarin

Keyword(s):

Charge Plasma ◽

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Investigation on the Effect of Gate Dielectric and Other Device Parameters on Digital Performance of Silicene Nanoribbon Tunnel FET

IEEE Transactions on Electron Devices ◽

10.1109/ted.2020.2992016 ◽

2020 ◽

Vol 67 (7) ◽

pp. 2966-2973 ◽

Author(s):

Niraj Kumar Singh ◽

Manodipan Sahoo

Keyword(s):

Gate Dielectric ◽

Digital Performance ◽

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A novel self-aligned charge plasma Schottky barrier tunnel FET using work function engineering

Microelectronic Engineering ◽

10.1016/j.mee.2016.11.009 ◽

2017 ◽

Vol 168 ◽

pp. 67-75 ◽

Author(s):

Sangeeta Singh ◽

Arun Pratap Singh ◽

P.N. Kondekar

Keyword(s):

Work Function ◽

Schottky Barrier ◽

Charge Plasma ◽

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A Barrier Controlled Charge Plasma-Based TFET With Gate Engineering for Ambipolar Suppression and RF/Linearity Performance Improvement

IEEE Transactions on Electron Devices ◽

10.1109/ted.2017.2693679 ◽

2017 ◽

Vol 64 (6) ◽

pp. 2751-2757 ◽

Author(s):

Kaushal Nigam ◽

Sunil Pandey ◽

Pravin N. Kondekar ◽

Dheeraj Sharma ◽

Pawan Kumar Parte

Keyword(s):

Performance Improvement ◽

Charge Plasma ◽

Gate Engineering

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Performance improvement of Si Pocket-Tunnel FET with steep subthreshold slope and high ION/IOFF ratio

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology ◽

10.1109/icsict.2012.6467740 ◽

2012 ◽

Author(s):

Qianqian Huang ◽

Ru Huang ◽

Zhan Zhan ◽

Chunlei Wu ◽

Yingxin Qiu ◽

...

Keyword(s):

Performance Improvement ◽

Subthreshold Slope ◽

Steep Subthreshold Slope

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An analysis of interface trap charges to improve the reliability of a charge-plasma-based nanotube tunnel FET

Journal of Computational Electronics ◽

10.1007/s10825-021-01696-6 ◽

2021 ◽

Author(s):

Anju Gedam ◽

Bibhudendra Acharya ◽

Guru Prasad Mishra

Keyword(s):

Interface Trap ◽

Charge Plasma ◽

A Charge ◽

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A SiGe-Source Doping-Less Double-Gate Tunnel FET: Design and Analysis Based on Charge Plasma Technique with Enhanced Performance

Silicon ◽

10.1007/s12633-021-01030-6 ◽

2021 ◽

Author(s):

Varun Mishra ◽

Yogesh Kumar Verma ◽

Santosh Kumar Gupta ◽

Vikas Rathi

Keyword(s):

Double Gate ◽

Charge Plasma ◽

Plasma Technique ◽

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Insights into interlayer tunnel FET performance improvement: Lessons learned from graphene hexagonal boron nitride heterostructures

2016 74th Annual Device Research Conference (DRC) ◽

10.1109/drc.2016.7548442 ◽

2016 ◽

Author(s):

S. Kang ◽

N. Prasad ◽

H. C. P. Movva ◽

A. Rai ◽

K. Kim ◽

...

Keyword(s):

Boron Nitride ◽

Performance Improvement ◽

Hexagonal Boron Nitride ◽

Lessons Learned ◽

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Investigation of Charge-plasma Based Dopingless Tunnel FET for Analog/RF and Linear Applications

Silicon ◽

10.1007/s12633-021-01514-5 ◽

2021 ◽

Author(s):

Suruchi Sharma ◽

Rikmantra Basu ◽

Baljit Kaur

Keyword(s):

Charge Plasma ◽

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