Fabrication and characterization of ZnO nanowire transistors with organic polymer as a dielectric layer

We report the fabrication and electrical characterization of ZnO nanowire field effect transistors (FETs). Dielectrophoresis technique was used to directly align ZnO nanowires between lithographically prepatterned source and drain electrodes, and spin-coated polyvinylphenol (PVP) polymer thin layer was used as a gate dielectric layer in "top-gate" FET device configuration. The electrical characteristics of the top-gate ZnO nanowire FETs were found to be comparable to the conventional "bottom-gate" nanowire FETs with a SiO2 gate dielectric layer, suggesting the directly-assembled nanowire FET with a polymer gate dielectric layer is a useful device structure of nanowire FETs.

Download Full-text

Fabrication and characterization of well-aligned, high density ZnO nanowire arrays and their realizations in Schottky device applications using a two-step approach

Journal of Materials Chemistry ◽

10.1039/c1jm10496a ◽

2011 ◽

Vol 21 (20) ◽

pp. 7090 ◽

Cited By ~ 30

Author(s):

Liaoyong Wen ◽

Kin Mun Wong ◽

Yaoguo Fang ◽

Minghong Wu ◽

Yong Lei

Keyword(s):

High Density ◽

Nanowire Arrays ◽

Zno Nanowire ◽

Zno Nanowire Arrays ◽

Device Applications ◽

Fabrication And Characterization ◽

Schottky Device

Download Full-text

Fabrication and Characterization of NOR-Type Tri-Gate Flash Memory with Improved Inter-Poly Dielectric Layer by Rapid Thermal Oxidation

Japanese Journal of Applied Physics ◽

10.7567/jjap.51.06fe19 ◽

2012 ◽

Vol 51 (6S) ◽

pp. 06FE19 ◽

Cited By ~ 1

Author(s):

Takahiro Kamei ◽

Yongxun Liu ◽

Takashi Matsukawa ◽

Kazuhiko Endo ◽

Shinichi O'uchi ◽

...

Keyword(s):

Thermal Oxidation ◽

Flash Memory ◽

Dielectric Layer ◽

Rapid Thermal Oxidation ◽

Fabrication And Characterization

Download Full-text

Fabrication and characterization of ZnO nanowire structure on flexible substrate with different solution molarities

10.1117/12.863917 ◽

2010 ◽

Author(s):

Kyu-Hang Lee ◽

Shin Hur ◽

Wan-Doo Kim ◽

Hongsoo Choi

Keyword(s):

Flexible Substrate ◽

Zno Nanowire ◽

Fabrication And Characterization ◽

Nanowire Structure

Download Full-text

Fabrication and Characterization of NOR-Type Tri-Gate Flash Memory with Improved Inter-Poly Dielectric Layer by Rapid Thermal Oxidation

Japanese Journal of Applied Physics ◽

10.1143/jjap.51.06fe19 ◽

2012 ◽

Vol 51 ◽

pp. 06FE19 ◽

Cited By ~ 6

Author(s):

Takahiro Kamei ◽

Yongxun Liu ◽

Takashi Matsukawa ◽

Kazuhiko Endo ◽

Shinichi O'uchi ◽

...

Keyword(s):

Thermal Oxidation ◽

Flash Memory ◽

Dielectric Layer ◽

Rapid Thermal Oxidation ◽

Fabrication And Characterization

Download Full-text

Fabrication of Poly-Silicon Nano-Wire Transistors on Plastic Substrates

Journal of Nanoscience and Nanotechnology ◽

10.1166/jnn.2007.18093 ◽

2007 ◽

Vol 7 (11) ◽

pp. 4150-4153

Author(s):

ChangMin Park ◽

SeHan Lee ◽

MinSu Choi ◽

MyungGil Kang ◽

YoungChai Jung ◽

...

Keyword(s):

Sacrificial Layer ◽

Flexible Substrates ◽

Si Substrate ◽

Plastic Substrates ◽

Si Nanowire ◽

Nanowire Transistors ◽

New Process ◽

Curing Condition ◽

Fabrication And Characterization

We report the fabrication and characterization of poly-Si nanowire transistors on flexible substrates. The nanowire transistors are fabricated on a SiO2/Si substrate using conventional CMOS processes, and then they are transferred onto polyimide substrates. The transfer process is performed by spin-coating of polyimide, curing (annealing) of the polyimide layer, and removal of the SiO2 sacrificial layer. The optimized curing condition results in the maximum bending of 150° with full recovery. The nanowire transistors exhibit transistor characteristics as a function of the backgate bias. Our new process can be applied to the fabrication of Si-nanowire transistors with larger mobilities.

Download Full-text