The effect of line width on stress-induced voiding in Cu dual damascene interconnects

2006 ◽  
Vol 504 (1-2) ◽  
pp. 298-301 ◽  
Author(s):  
W. Shao ◽  
Z.H. Gan ◽  
S.G. Mhaisalkar ◽  
Zhong Chen ◽  
Hongyu Li
Keyword(s):  
Line Width ◽  
Dual Damascene ◽  
Damascene Interconnects

Dual Damascene Process for FatWires in Copper/FSG Technology

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  
Keyword(s):  
Line Width ◽  
Lower Cost ◽  
Process Window ◽  
Cmos Process ◽  
Dual Damascene ◽  
Damascene Process ◽  
Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

Novel Cu reflow seed process for Cu/low-k 64nm pitch dual damascene interconnects and beyond

2012 ◽  
Author(s):  
K. Motoyama ◽  
O. van der Straten ◽  
H. Tomizawa ◽  
J. Maniscalco ◽  
S.T. Chen
Keyword(s):  
Dual Damascene ◽  
Damascene Interconnects ◽  
Low K

scholarly journals Fatal Void Size Comparisons in Via-Below and Via-Above Cu Dual-Damascene Interconnects

2004 ◽  
Vol 812 ◽  
Author(s):  
Z. -S. Choi ◽  
C. L. Gan ◽  
F. Wei ◽  
C. V. Thompson ◽  
J. H. Lee ◽  
...  
Keyword(s):  
Numerical Simulation ◽  
Failure Mechanisms ◽  
Simulation Tool ◽  
Void Size ◽  
Dual Damascene ◽  
Preferential Nucleation ◽  
Failure Correlation ◽  
Void Volumes ◽  
Damascene Interconnects ◽  
Critical Void

AbstractThe median-times-to-failure (t50's) for straight dual-damascene via-terminated copper interconnect structures, tested under the same conditions, depend on whether the vias connect down to underlaying leads (metal 2, M2, or via-below structures) or connect up to overlaying leads (metal 1, M1, or via-above structures). Experimental results for a variety of line lengths, widths, and numbers of vias show higher t50's for M2 structures than for analogous M1 structures. It has been shown that despite this asymmetry in lifetimes, the electromigration drift velocity is the same for these two types of structures, suggesting that fatal void volumes are different in these two cases. A numerical simulation tool based on the Korhonen model has been developed and used to simulate the conditions for void growth and correlate fatal void sizes with lifetimes. These simulations suggest that the average fatal void size for M2 structures is more than twice the size of that of M1 structures. This result supports an earlier suggestion that preferential nucleation at the Cu/Si3N4 interface in both M1 and M2 structures leads to different fatal void sizes, because larger voids are required to span the line thickness in M2 structures while smaller voids below the base of vias can cause failures in M1 structures. However, it is also found that the fatal void sizes corresponding to the shortest-times-to-failure (STTF's) are similar for M1 and M2, suggesting that the voids that lead to the shortest lifetimes occur at or in the vias in both cases, where a void need only span the via to cause failure. Correlation of lifetimes and critical void volumes provides a useful tool for distinguishing failure mechanisms.

N5 technology node dual-damascene interconnects enabled using multi patterning

2017 ◽  
Author(s):  
B. Briggs ◽  
C. J. Wilson ◽  
K. Devriendt ◽  
M. H. van der Veen ◽  
S. Decoster ◽  
...  
Keyword(s):  
Technology Node ◽  
Dual Damascene ◽  
Damascene Interconnects

Via-Shape-Control for Copper Dual-Damascene Interconnects With Low-k Organic Film

2008 ◽  
Vol 21 (2) ◽  
pp. 256-262 ◽  
Author(s):  
Keizo Kinoshita ◽  
Munehiro Tada ◽  
Masayuki Hiroi ◽  
Kazutoshi Shiba ◽  
Takahiro Onodera ◽  
...  
Keyword(s):  
Shape Control ◽  
Organic Film ◽  
Dual Damascene ◽  
Damascene Interconnects ◽  
Low K

Effect of layout on electromigration characteristics in copper dual damascene interconnects

2014 ◽  
Vol 128 ◽  
pp. 19-23
Author(s):  
Y.L. Cheng ◽  
Y.M. Chang ◽  
Jihperng Leu ◽  
T.C. Bo ◽  
Y.L. Wang
Keyword(s):  
Dual Damascene ◽  
Damascene Interconnects

Slotted vias for dual damascene interconnects in 1 Gb DRAMs

2003 ◽  
Author(s):  
R.F. Schnabel ◽  
G. Bronner ◽  
L. Clevenger ◽  
D. Dobuzinsky ◽  
G. Costrini ◽  
...  
Keyword(s):  
Dual Damascene ◽  
Damascene Interconnects
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