Polarization effects in nitride semiconductor device structures and performance of modulation doped field effect transistors

In this paper, analytical modelling and performance analysis of novel device structures such as single gate SOI Tunnel Field Effect transistor (SG SOI TFET), Dual-Material Gate TFET (DMG TFET) and Dual Material Double Gate TFET (DMDG TFET) are proposed. The performance of the three devices is studied and compared in terms of surface potential, electric field and drain current. The DMDG TFET shows better performance in suppressing leakage current and enhancing ION current than the SG SOI TFET and DMG TFET. The analytical models of the devices are found to be in good agreement with the results obtained using two-dimensional TCAD device simulator.

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Behavior of contact-silicided TFSOI gate structures

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100172036 ◽

1994 ◽

Vol 52 ◽

pp. 860-861

Author(s):

N. David Theodore ◽

Juergen Foerstner ◽

Peter Fejes

Keyword(s):

Semiconductor Device ◽

Series Resistance ◽

Field Effect Transistors ◽

Silicon Layer ◽

Device Fabrication ◽

Silicon On Insulator ◽

Continuous Layer ◽

Buried Oxide ◽

Device Structures ◽

Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

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Chemically Sensitive Field-Effect Transistors and Chemiresistors: New Materials and Device Structures

Electroanalysis ◽

10.1002/elan.200403071 ◽

2004 ◽

Vol 16 (22) ◽

pp. 1837-1842 ◽

Cited By ~ 53

Author(s):

Howard?E. Katz

Keyword(s):

Field Effect ◽

Field Effect Transistors ◽

New Materials ◽

Device Structures

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New device structures for graphene nanoribbon field effect transistors

Materials Express ◽

10.1166/mex.2016.1304 ◽

2016 ◽

Vol 6 (3) ◽

pp. 265-270 ◽

Cited By ~ 1

Author(s):

Mahdiar Ghadiry ◽

Harith Ahmad ◽

Chong Wu Yi ◽

Asrulnizam Abd Manaf

Keyword(s):

Field Effect ◽

Field Effect Transistors ◽

Graphene Nanoribbon ◽

New Device ◽

Device Structures

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Low Temperature Device Processing Technology for II-VI Semiconductors

MRS Proceedings ◽

10.1557/proc-161-323 ◽

1989 ◽

Vol 161 ◽

Cited By ~ 1

Author(s):

D.L. Dreifus ◽

R.M. Kolbas ◽

B.P. Sneed ◽

J.F. Schetzina

Keyword(s):

Low Temperature ◽

Field Effect ◽

Field Effect Transistors ◽

Epitaxial Layers ◽

Processing Technologies ◽

Device Processing ◽

Device Structures ◽

Lift Off ◽

Processing Steps

ABSTRACTLow temperature (<60° C) processing technologies that avoid potentially damaging processing steps have been developed for devices fabricated from II-VI semiconductor epitaxial layers grown by photoassisted molecular beam epitaxy (MBE). These low temperature technologies include: 1) photolithography (1 µm geometries), 2) calibrated etchants (rates as low as 30 Å/s), 3) a metallization lift-off process employing a photoresist profiler, 4) an interlevel metal dielectric, and 5) an insulator technology for metal-insulator-semiconductor (MIS) structures. A number of first demonstration devices including field-effect transistors and p-n junctions have been fabricated from II-VI epitaxial layers grown by photoassisted MBE and processed using the technology described here. In this paper, two advanced device structures, processed at <60° C, will be presented: 1) CdTe:As-CdTe:In p-n junction detectors, grown in situ by photoassisted MBE, and 2) HgCdTe-HgTe-CdZnTe quantum-well modulation-doped field-effect transistors (MODFETs).

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