Comparative Performance Analysis of Multi Gate Tunnel Field Effect Transistors

2016 ◽  
Vol 41 ◽  
pp. 1-8 ◽  
Author(s):  
T.S. Arun Samuel ◽  
M. Karthigai Pandian
Keyword(s):  
Performance Analysis ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Analytical Models ◽  
Comparative Performance ◽  
Novel Device ◽  
Device Structures ◽  
And Performance ◽  
Dual Material

In this paper, analytical modelling and performance analysis of novel device structures such as single gate SOI Tunnel Field Effect transistor (SG SOI TFET), Dual-Material Gate TFET (DMG TFET) and Dual Material Double Gate TFET (DMDG TFET) are proposed. The performance of the three devices is studied and compared in terms of surface potential, electric field and drain current. The DMDG TFET shows better performance in suppressing leakage current and enhancing ION current than the SG SOI TFET and DMG TFET. The analytical models of the devices are found to be in good agreement with the results obtained using two-dimensional TCAD device simulator.

Comparative Performance Analysis of Nanowire and Nanotube Field Effect Transistors

2021 ◽  
pp. 54-70
Author(s):  
Raj Kumar ◽  
Shashi Bala ◽  
Arvind Kumar
Keyword(s):  
Performance Analysis ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Ballistic Transport ◽  
High Mobility ◽  
Short Channel Effects ◽  
Short Channel ◽  
Comparative Performance ◽  
Channel Effects ◽  
And Performance

To have enhanced drive current and diminish short channel effects, planer MOS transistors have migrated from single-gate devices to three-dimensional multi-gate MOSFETs. The gate-all-around nanowire field-effect transistor (GAA NWFET) and nanotube or double gate-all-around field-effect transistors (DGGA-NTFET) have been proposed to deal with short channel effects and performance relates issues. Nanowire and nanotube-based field-effect transistors can be considered as leading candidates for nanoscale devices due to their superior electrostatic controllability, and ballistic transport properties. In this work, the performance of GAA NWFETs and DGAA-NT FETs will be analyzed and compared. III-V semiconductor materials as a channel will also be employed due to their high mobility over silicon. Performance analysis of junctionless nanowire and nanotube FETs will also be compared and presented.

scholarly journals Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

Nanomaterials ◽  
2019 ◽  
Vol 9 (2) ◽  
pp. 181 ◽  
Author(s):  
Hongliang Lu ◽  
Bin Lu ◽  
Yuming Zhang ◽  
Yimen Zhang ◽  
Zhijun Lv
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Current Model ◽  
Tunneling Current ◽  
Drain Current ◽  
Device Structure ◽  
Band Engineering ◽  
Novel Device ◽  
Analytical Potential ◽  
Good Agreement

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

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