Energy-Efficient Tunneling Field-Effect Transistors for Low-Power Device Applications: Challenges and Opportunities

2020 ◽  
Vol 12 (42) ◽  
pp. 47127-47163
Author(s):  
Ghazanfar Nazir ◽  
Adeela Rehman ◽  
Soo-Jin Park
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Power Device ◽  
Tunneling Field Effect Transistors ◽  
Challenges And Opportunities ◽  
Device Applications

scholarly journals A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 223 ◽  
Author(s):  
Yannan Zhang ◽  
Ke Han ◽  
and Jiawei Li
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Future Generation ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Ultra Low Power

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

Low voltage and high ON/OFF ratio field-effect transistors based on CVD MoS2 and ultra high-k gate dielectric PZT

Nanoscale ◽  
2015 ◽  
Vol 7 (19) ◽  
pp. 8695-8700 ◽  
Author(s):  
Changjian Zhou ◽  
Xinsheng Wang ◽  
Salahuddin Raju ◽  
Ziyuan Lin ◽  
Daniel Villaroman ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Field Effect Transistors ◽  
Power Device ◽  
Enhancement Mode ◽  
High K ◽  
High K Gate Dielectric

Ultra high-k dielectric enables low-voltage enhancement-mode MoS2 transistor with high ON/OFF ratio, leading to low-power device.

Effects of dual-spacer dielectrics on low-power and high-speed performance of sub-10 nm tunneling field-effect transistors

2016 ◽  
Vol 55 (6S1) ◽  
pp. 06GG02 ◽  
Author(s):  
Young Jun Yoon ◽  
Jae Hwa Seo ◽  
Seongjae Cho ◽  
Hyuck-In Kwon ◽  
Jung-Hee Lee ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistors ◽  
Tunneling Field Effect Transistors ◽  
Speed Performance

scholarly journals Device performance limits and negative capacitance of monolayer GeSe and GeTe tunneling field effect transistors

RSC Advances ◽  
2020 ◽  
Vol 10 (27) ◽  
pp. 16071-16078 ◽  
Author(s):  
Peipei Xu ◽  
Jiakun Liang ◽  
Hong Li ◽  
Fengbin Liu ◽  
Jun Tie ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Device Performance ◽  
Negative Capacitance ◽  
Performance Limits ◽  
Tunneling Field Effect Transistors

The ML GeSe and GeTe NCTFETs fulfill the ITRS low power and high performance devices, respectively, at the “4/3” node range.

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