scholarly journals Entanglement across separate silicon dies in a modular superconducting qubit device

2021 ◽  
Vol 7 (1) ◽  
Author(s):  
Alysson Gold ◽  
J. P. Paquette ◽  
Anna Stockklauser ◽  
Matthew J. Reagor ◽  
M. Sohaib Alam ◽  
...  
Keyword(s):  
Solid State ◽  
Integrated Circuits ◽  
Large Scale ◽  
Fault Tolerant ◽  
Bell Inequality ◽  
Building Blocks ◽  
Superconducting Qubit ◽  
Modular Architecture ◽  
Near Term ◽  
Qubit Gate

AbstractAssembling future large-scale quantum computers out of smaller, specialized modules promises to simplify a number of formidable science and engineering challenges. One of the primary challenges in developing a modular architecture is in engineering high fidelity, low-latency quantum interconnects between modules. Here we demonstrate a modular solid state architecture with deterministic inter-module coupling between four physically separate, interchangeable superconducting qubit integrated circuits, achieving two-qubit gate fidelities as high as 99.1 ± 0.5% and 98.3 ± 0.3% for iSWAP and CZ entangling gates, respectively. The quality of the inter-module entanglement is further confirmed by a demonstration of Bell-inequality violation for disjoint pairs of entangled qubits across the four separate silicon dies. Having proven out the fundamental building blocks, this work provides the technological foundations for a modular quantum processor: technology which will accelerate near-term experimental efforts and open up new paths to the fault-tolerant era for solid state qubit architectures.

scholarly journals Engineering the quantum-classical interface of solid-state qubits

2015 ◽  
Vol 1 (1) ◽  
Author(s):  
David J Reilly
Keyword(s):  
Quantum Information ◽  
Solid State ◽  
Degrees Of Freedom ◽  
Technology Development ◽  
Fault Tolerant ◽  
Building Blocks ◽  
Experimental Physicist ◽  
And Mathematics ◽  
Classical Control ◽  
And Control

AbstractSpanning a range of hardware platforms, the building-blocks of quantum processors are today sufficiently advanced to begin work on scaling-up these systems into complex quantum machines. A key subsystem of all quantum machinery is the interface between the isolated qubits that encode quantum information and the classical control and readout technology needed to operate them. As few-qubit devices are combined to construct larger, fault-tolerant quantum systems in the near future, the quantum-classical interface will pose new challenges that increasingly require approaches from the engineering disciplines in combination with continued fundamental advances in physics, materials and mathematics. This review describes the subsystems comprising the quantum-classical interface from the viewpoint of an engineer, experimental physicist or student wanting to enter the field of solid-state quantum information technology. The fundamental signalling operations of readout and control are reviewed for a variety of qubit platforms, including spin systems, superconducting implementations and future devices based on topological degrees-of-freedom. New engineering opportunities for technology development at the boundary between qubits and their control hardware are identified, transversing electronics to cryogenics.

scholarly journals Reconfigurable Integrated Optoelectronics

2011 ◽  
Vol 2011 ◽  
pp. 1-15 ◽  
Author(s):  
Richard Soref
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
High Volume ◽  
Building Blocks ◽  
Information Storage ◽  
Microwave Antenna ◽  
Optical Logic ◽  
Lattice Filters ◽  
Optoelectronic Integrated Circuits ◽  
Scale Matrix

Integrated optics today is based upon chips of Si and InP. The future of this chip industry is probably contained in the thrust towards optoelectronic integrated circuits (OEICs) and photonic integrated circuits (PICs) manufactured in a high-volume foundry. We believe that reconfigurable OEICs and PICs, known as ROEICs and RPICs, constitute the ultimate embodiment of integrated photonics. This paper shows that any ROEIC-on-a-chip can be decomposed into photonic modules, some of them fixed and some of them changeable in function. Reconfiguration is provided by electrical control signals to the electro-optical building blocks. We illustrate these modules in detail and discuss 3D ROEIC chips for the highest-performance signal processing. We present examples of our module theory for RPIC optical lattice filters already constructed, and we propose new ROEICs for directed optical logic, large-scale matrix switching, and 2D beamsteering of a phased-array microwave antenna. In general, large-scale-integrated ROEICs will enable significant applications in computing, quantum computing, communications, learning, imaging, telepresence, sensing, RF/microwave photonics, information storage, cryptography, and data mining.

scholarly journals Integration of single photon emitters in 2D layered materials with a silicon nitride photonic chip

2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Frédéric Peyskens ◽  
Chitraleema Chakraborty ◽  
Muhammad Muneeb ◽  
Dries Van Thourhout ◽  
Dirk Englund
Keyword(s):  
Silicon Nitride ◽  
Integrated Circuits ◽  
Large Scale ◽  
Single Photon ◽  
Transition Metal Dichalcogenides ◽  
Building Blocks ◽  
Single Photon Emitters ◽  
Metal Dichalcogenides ◽  
On Chip ◽  
Scale Integration

Abstract Photonic integrated circuits (PICs) enable the miniaturization of optical quantum circuits because several optic and electronic functionalities can be added on the same chip. Integrated single photon emitters (SPEs) are central building blocks for such quantum photonic circuits. SPEs embedded in 2D transition metal dichalcogenides have some unique properties that make them particularly appealing for large-scale integration. Here we report on the integration of a WSe2 monolayer onto a Silicon Nitride (SiN) chip. We demonstrate the coupling of SPEs with the guided mode of a SiN waveguide and study how the on-chip single photon extraction can be maximized by interfacing the 2D-SPE with an integrated dielectric cavity. Our approach allows the use of optimized PIC platforms without the need for additional processing in the SPE host material. In combination with improved wafer-scale CVD growth of 2D materials, this approach provides a promising route towards scalable quantum photonic chips.

Some applications of electron beam microanalysis techniques in VLSI process evaluation

1983 ◽  
Vol 41 ◽  
pp. 160-161
Author(s):  
Simon Thomas
Keyword(s):  
Integrated Circuits ◽  
Process Evaluation ◽  
Large Scale ◽  
Technology Development ◽  
Analytical Techniques ◽  
Successful Implementation ◽  
Analysis Of Failures ◽  
Characterization Of Materials ◽  
Circuits Vlsi

Trends in the technology development of very large scale integrated circuits (VLSI) have been in the direction of higher density of components with smaller dimensions. The scaling down of device dimensions has been not only laterally but also in depth. Such efforts in miniaturization bring with them new developments in materials and processing. Successful implementation of these efforts is, to a large extent, dependent on the proper understanding of the material properties, process technologies and reliability issues, through adequate analytical studies. The analytical instrumentation technology has, fortunately, kept pace with the basic requirements of devices with lateral dimensions in the micron/ submicron range and depths of the order of nonometers. Often, newer analytical techniques have emerged or the more conventional techniques have been adapted to meet the more stringent requirements. As such, a variety of analytical techniques are available today to aid an analyst in the efforts of VLSI process evaluation. Generally such analytical efforts are divided into the characterization of materials, evaluation of processing steps and the analysis of failures.

Electron microscopy study of reactively sputter-deposited Ti/N films on silicon

1992 ◽  
Vol 50 (2) ◽  
pp. 1362-1363
Author(s):  
V. C. Kannan ◽  
A. K. Singh ◽  
R. B. Irwin ◽  
S. Chittipeddi ◽  
F. D. Nkansah ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Hexagonal Phase ◽  
Microscopy Study ◽  
Electron Microscopy Study ◽  
Process Conditions ◽  
Tin Films ◽  
Wide Range ◽  
Fcc Phase ◽  
Circuits Vlsi

Titanium nitride (TiN) films have historically been used as diffusion barrier between silicon and aluminum, as an adhesion layer for tungsten deposition and as an interconnect material etc. Recently, the role of TiN films as contact barriers in very large scale silicon integrated circuits (VLSI) has been extensively studied. TiN films have resistivities on the order of 20μ Ω-cm which is much lower than that of titanium (nearly 66μ Ω-cm). Deposited TiN films show resistivities which vary from 20 to 100μ Ω-cm depending upon the type of deposition and process conditions. TiNx is known to have a NaCl type crystal structure for a wide range of compositions. Change in color from metallic luster to gold reflects the stabilization of the TiNx (FCC) phase over the close packed Ti(N) hexagonal phase. It was found that TiN (1:1) ideal composition with the FCC (NaCl-type) structure gives the best electrical property.

The Structure and Properties of MoSi2 Thin Film in Mos Process

1980 ◽  
Vol 38 ◽  
pp. 326-327
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Process Development ◽  
Structure And Properties ◽  
Metal Silicides ◽  
High Oxidation ◽  
Important Approach ◽  
High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

Characterization of Interconnect Defects Using Scanning Thermal Conductivity Microscopy

2004 ◽  
Author(s):  
H.W. Ho ◽  
J.C.H. Phang ◽  
A. Altes ◽  
L.J. Balk
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
Large Scale

Abstract In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.

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