Fabricating flexible wafer-size inorganic semiconductor devices

2020 ◽  
Vol 8 (6) ◽  
pp. 1915-1922 ◽  
Author(s):  
Yunhuan Yuan ◽  
Senpei Xie ◽  
Chaogang Ding ◽  
Xianbiao Shi ◽  
Jie Xu ◽  
...  

In this work, we proposed a scheme to obtain flexible wafer-size inorganic semiconductor devices and discussed their mechanism of this super flexibility.

2018 ◽  
Vol 15 (4) ◽  
pp. 388 ◽  
Author(s):  
D. Beljonne ◽  
J. Cornil ◽  
J. L. Brèdas ◽  
V. Coropceanu

<span>Inorganic semiconductor devices such as transistors have been instrumental in shaping the development of our society of information and communication. Recently, the electronics and photonics technologies have opened their materials base to organics, in particular p-conjugated oligomers and polymers. The goal with organics-based devices is not necessarily to attain or exceed the level of performance of inorganic semiconductor technologies...</span>


2010 ◽  
Vol 50 (1) ◽  
pp. 10401 ◽  
Author(s):  
Ö. Güllü ◽  
S. Asubay ◽  
M. Biber ◽  
T. Kiliçoglu ◽  
A. Türüt

2021 ◽  
Author(s):  
Jung-In Yoon ◽  
Chang-Hyo Son ◽  
Sung-Hoon Seol ◽  
Ji-Hoon Yoon

The growth of the semiconductor market and advancement of manufacturing technology have led to an increase in wafer size and highly integrated semiconductor devices. The temperature of the supplied cooling medium from the chiller that removes the heat produced in the semiconductor manufacturing process is required to be at a lower level because of the high integration. The Joule-Thomson cooling cycle, which uses a mixed refrigerant (MR) to produce the cooling medium at a level of −100°C required for the semiconductor process, has recently gained attention. When a MR is used, the chiller’s performance is heavily influenced by the composition and proportions of the refrigerant charged to the chiller system. Therefore, this paper introduces a cooling cycle that uses an MR to achieve the required low temperature of −100°C in the semiconductor manufacturing process and provides the results of simple experiments to determine the effects of different MR compositions.


Author(s):  
Peter Pegler ◽  
N. David Theodore ◽  
Ming Pan

High-pressure oxidation of silicon (HIPOX) is one of various techniques used for electrical-isolation of semiconductor-devices on silicon substrates. Other techniques have included local-oxidation of silicon (LOCOS), poly-buffered LOCOS, deep-trench isolation and separation of silicon by implanted oxygen (SIMOX). Reliable use of HIPOX for device-isolation requires an understanding of the behavior of the materials and structures being used and their interactions under different processing conditions. The effect of HIPOX-related stresses in the structures is of interest because structuraldefects, if formed, could electrically degrade devices.This investigation was performed to study the origin and behavior of defects in recessed HIPOX (RHIPOX) structures. The structures were exposed to a boron implant. Samples consisted of (i) RHlPOX'ed strip exposed to a boron implant, (ii) recessed strip prior to HIPOX, but exposed to a boron implant, (iii) test-pad prior to HIPOX, (iv) HIPOX'ed region away from R-HIPOX edge. Cross-section TEM specimens were prepared in the <110> substrate-geometry.


Author(s):  
Terrence Reilly ◽  
Al Pelillo ◽  
Barbara Miner

The use of transmission electron microscopes (TEM) has proven to be very valuable in the observation of semiconductor devices. The need for high resolution imaging becomes more important as the devices become smaller and more complex. However, the sample preparation for TEM observation of semiconductor devices have generally proven to be complex and time consuming. The use of ion milling machines usually require a certain degree of expertise and allow a very limited viewing area. Recently, the use of an ultra high resolution "immersion lens" cold cathode field emission scanning electron microscope (CFESEM) has proven to be very useful in the observation of semiconductor devices. Particularly at low accelerating voltages where compositional contrast is increased. The Hitachi S-900 has provided comparable resolution to a 300kV TEM on semiconductor cross sections. Using the CFESEM to supplement work currently being done with high voltage TEMs provides many advantages: sample preparation time is greatly reduced and the observation area has also been increased to 7mm. The larger viewing area provides the operator a much greater area to search for a particular feature of interest. More samples can be imaged on the CFESEM, leaving the TEM for analyses requiring diffraction work and/or detecting the nature of the crystallinity.


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