Ultra-Low Temperature Chillers for Semiconductor Manufacturing Process

The growth of the semiconductor market and advancement of manufacturing technology have led to an increase in wafer size and highly integrated semiconductor devices. The temperature of the supplied cooling medium from the chiller that removes the heat produced in the semiconductor manufacturing process is required to be at a lower level because of the high integration. The Joule-Thomson cooling cycle, which uses a mixed refrigerant (MR) to produce the cooling medium at a level of −100°C required for the semiconductor process, has recently gained attention. When a MR is used, the chiller’s performance is heavily influenced by the composition and proportions of the refrigerant charged to the chiller system. Therefore, this paper introduces a cooling cycle that uses an MR to achieve the required low temperature of −100°C in the semiconductor manufacturing process and provides the results of simple experiments to determine the effects of different MR compositions.

Adapting M2 silicon half-wafers processing on industrial-scale equipment dedicated to 4″ solar technology

Purpose The purpose of this study is to address the issue of technology equipment formerly dedicated to the process of 4- and even 5-inch photovoltaic cells and whose use has become critical with the evolution of silicon wafer size standards (M2–M10). Fortunately, the recent concept of 6'' half-cut cell with its many advantages appears promising insofar as it offers the possibility of further extend the use of costly, still operational process equipment, but doomed to obsolescence. Design/methodology/approach In the background of a detailed Al-BSF process, the authors show how to experimentally adapt specific accessories and arrange 6” half-wafers to enable the upgrade of a complete industrial process of silicon solar cells at a lower cost. Step by step, the implementation of the processes for the two wafer sizes (4” wafers and 6” half wafers) is compared and analyzed in terms of performance and throughput. Findings Globally, the same process effectiveness is observed for both types of wafers with slightly better sheet resistance uniformity for the thermal diffusion carried out on the half wafers; however, the horizontal arrangement of the wafer carriers in the diffusion and the plasma-enhanced chemical vapor deposition tubes limits the thermal balance regarding the total number of cells processed per batch. Originality/value In terms of the development of prototypes on a preindustrial scale, this paves the way to further continue operating outdated equipment for high-performance processes (passivated emitter and rear contact, Tunnel oxide passivated contact (TOPCon)), while complying with current standards for silicon wafers up to M10 format.

Engineering grain boundaries at the 2D limit for the hydrogen evolution reaction

Atom-thin transition metal dichalcogenides (TMDs) have emerged as fascinating materials and key structures for electrocatalysis. So far, their edges, dopant heteroatoms and defects have been intensively explored as active sites for the hydrogen evolution reaction (HER) to split water. However, grain boundaries (GBs), a key type of defects in TMDs, have been overlooked due to their low density and large structural variations. Here, we demonstrate the synthesis of wafer-size atom-thin TMD films with an ultra-high-density of GBs, up to ~1012 cm−2. We propose a climb and drive 0D/2D interaction to explain the underlying growth mechanism. The electrocatalytic activity of the nanograin film is comprehensively examined by micro-electrochemical measurements, showing an excellent hydrogen-evolution performance (onset potential: −25 mV and Tafel slope: 54 mV dec−1), thus indicating an intrinsically high activation of the TMD GBs.

Fabricating flexible wafer-size inorganic semiconductor devices

In this work, we proposed a scheme to obtain flexible wafer-size inorganic semiconductor devices and discussed their mechanism of this super flexibility.