Charge‐plasma‐based super‐steep negative capacitance junctionless tunnel field effect transistor: design and performance

2014 ◽  
Vol 50 (25) ◽  
pp. 1963-1965 ◽  
Author(s):  
S. Singh ◽  
P. Pal ◽  
P. N. Kondekar
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Negative Capacitance ◽  
Charge Plasma ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
And Performance

scholarly journals Design Optimization of Nanotube Tunnel Field-Effect Transistor with Bias-Induced Electron-Hole Bilayer

2021 ◽  
Author(s):  
Xueke Wang ◽  
Yabin Sun ◽  
Ziyu Liu ◽  
Yun Liu ◽  
Xiaojin Li ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Dynamic Performance ◽  
Drain Current ◽  
Electron Hole ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
And Performance ◽  
First Time ◽  
Tcad Simulations

Abstract In this paper, a novel nanotube tunneling field-effect transistor (NT-TFET) with bias-induced electron-hole bilayer (EHBNT-TFET) is proposed for the first time. By the intentional misalignment and an asymmetric bias configuration of the inner-gate and outer-gate, the line tunneling takes place inside the channel, significantly improving the tunneling rate and area. The device principle and performance are investigated by calibrated 3-D TCAD simulations. Compared to the conventional NT-TFET, the proposed EHBNT-TFET exhibits an increased ON-state current (ION) about 57.2 times and a sub-60 mV/dec subthreshold swing for seven orders of magnitude of drain current. Furthermore, the increased ION and reduced gate capacitance achieve improved dynamic performance. Compared with conventional NT-TFET, the intrinsic delay decreased about 142 times is obtained in EHBNT-TFET.

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