Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction

2010 ◽  
Vol 4 (4) ◽  
pp. 317-324
Author(s):  
W.-D. Tseng ◽  
R.-B. Lin ◽  
L.-J. Lee
2017 ◽  
Vol 10 (04) ◽  
pp. 710-717
Author(s):  
A. Ahmad ◽  
D. Al Abri ◽  
S. S. Al Busaidi ◽  
M. M. Bait-Suwailam

The authors show that in a Built-In Self-Test (BIST) technique, based on linear-feedback shift registers, when the feedback connections in pseudo-random test-sequence generator and signature analyzer are images of each other and corresponds to primitive characteristic polynomial then behaviors of faults masking remains identical. The simulation results of single stuck-at faults show how the use of such feedback connections in pseudo-random test-sequence generator and signature analyzer yields to mask the same faults.


2014 ◽  
Vol 11 (2) ◽  
pp. 1 ◽  
Author(s):  
A Ahmad ◽  
A Al Maashri

The study of the length of pseudo-random binary sequences generated by Linear- Feedback Shift Registers (LFSRs) plays an important role in the design approaches of built-in selftest, cryptosystems, and other applications. However, certain LFSR structures might not be appropriate in some situations. Given that determining the length of generated pseudo-random binary sequence is a complex task, therefore, before using an LFSR structure, it is essential to investigate the length and the properties of the sequence. This paper investigates some conditions and LFSR’s structures, which restrict the pseudo-random binary sequences’ generation to a certain fixed length. The outcomes of this paper are presented in the form of theorems, simulations, and analyses. We believe that these outcomes are of great importance to the designers of built-in self-test equipment, cryptosystems, and other applications such as radar, CDMA, error correction, and Monte Carlo simulation. 


VLSI Design ◽  
2000 ◽  
Vol 11 (2) ◽  
pp. 149-159
Author(s):  
Chien-In Henry Chen ◽  
Yingjie Zhou

Recently a multiple-sequence test generator was presented based on two-dimensional linear feedback shift registers (2-D LFSR). This generator can generate a set of precomputed test vectors obtained by an ATPG tool for detecting random-pattern-resistant faults and particular hard-to-detect faults. In addition, it can generate better random patterns than a conventional LFSR. In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults and a corresponding set of test vectors detecting these faults, the corresponding test pattern generator is determined automatically. A synthesis procedure of designing this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators.


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