Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

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Nb2O5 and Ti-Doped Nb2O5 Charge Trapping Nano-Layers Applied in Flash Memory

Nanomaterials ◽

10.3390/nano8100799 ◽

2018 ◽

Vol 8 (10) ◽

pp. 799 ◽

Cited By ~ 1

Author(s):

Jer Wang ◽

Chyuan Kao ◽

Chien Wu ◽

Chun Lin ◽

Chih Lin

Keyword(s):

Flash Memory ◽

Charge Trapping ◽

Memory Device ◽

Dielectric Constants ◽

Oxide Semiconductor ◽

Flat Band ◽

Hysteresis Curve ◽

Band Shift ◽

K Value ◽

High K

High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb2O5 and Ti-doped Nb2O5(TiNb2O7) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆VFB) window of the TiNb2O7 charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb2O7 nano-layer is because of a better electrical and structural performance, compared to the Nb2O5 nano-layer.

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Novel multi-bit SONOS type flash memory using a high-k charge trapping layer

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221069 ◽

2004 ◽

Cited By ~ 27

Author(s):

T. Sugizaki ◽

M. Kobayashi ◽

M. Ishidao ◽

H. Minakata ◽

M. Yamaguchi ◽

...

Keyword(s):

Flash Memory ◽

Charge Trapping ◽

High K

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The Influence of Defects and Impurities on Electrical Properties of High-k Dielectrics

Materials Science Forum ◽

10.4028/www.scientific.net/msf.608.55 ◽

2008 ◽

Vol 608 ◽

pp. 55-109 ◽

Cited By ~ 3

Author(s):

Jaroslaw Dąbrowski ◽

Seiichi Miyazaki ◽

S. Inumiya ◽

G. Kozłowski ◽

G. Lippert ◽

...

Keyword(s):

Electrical Properties ◽

Carrier Transport ◽

Dielectric Material ◽

Electrical Breakdown ◽

Charge Trapping ◽

Basic Knowledge ◽

Dielectric Films ◽

Low Leakage ◽

High K ◽

High K Dielectric

Electrical properties of thin high-k dielectric films are influenced (or even governed) by the presence of macroscopic, microscopic and atomic-size defects. For most applications, a structurally perfect dielectric material with moderate parameters would have sufficiently low leakage and sufficiently long lifetime. But defects open new paths for carrier transport, increasing the currents by orders of magnitude, causing instabilities due to charge trapping, and promoting the formation of defects responsible for electrical breakdown events and for the failure of the film. We discuss how currents flow across the gate stack and how damage is created in the material. We also illustrate the contemporary basic knowledge on hazardous defects (including certain impurities) in high-k dielectrics using the example of a family of materials based on Pr oxides. As an example of the influence of stoichiometry on the electrical pa-rameters of the dielectric, we analyze the effect of nitrogen incorporation into ultrathin Hf silicate films.

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SELF-CONSISTENT SIMULATION OF QUANTUM DOT FLASH MEMORY DEVICE WITH SiO2 AND HfO2 DIELECTRICS

International Journal of Nanoscience ◽

10.1142/s0219581x05003036 ◽

2005 ◽

Vol 04 (02) ◽

pp. 171-178

Author(s):

CHEE CHING CHONG ◽

KAI HONG ZHOU ◽

PING BAI ◽

ER PING LI ◽

GANESH S. SAMUDRA

Keyword(s):

Quantum Dot ◽

Flash Memory ◽

Gate Dielectric ◽

Tunneling Current ◽

Memory Device ◽

Device Structure ◽

Dielectric Thickness ◽

Silicon Quantum Dot ◽

High K ◽

Self Consistent

Flash memory structure in which a silicon quantum dot embedded in the gate dielectric region between the channel and the control gate is considered. A self-consistent simulation for such memory devices is performed and aims to understand the relationship between the device structure and the meaningful quantities, as required for an efficient device operation. In this study, both the traditional SiO2 and HfO2 high-k dielectrics are being explored, and their results are compared and contrasted. In particular, the superiority of HfO2 over the SiO2 is demonstrated through various interlocking investigations on the relationships between the tunneling current, dielectric thickness, barrier height, programming and retention times.

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