Diamond logic inverter with enhancement-mode metal-insulator-semiconductor field effect transistor

2014 ◽  
Vol 105 (8) ◽  
pp. 082110 ◽  
Author(s):  
J. W. Liu ◽  
M. Y. Liao ◽  
M. Imura ◽  
E. Watanabe ◽  
H. Oosato ◽  
...  
2000 ◽  
Vol 622 ◽  
Author(s):  
P. Chen ◽  
R. Zhang ◽  
Y.G. Zhou ◽  
S.Y. Xie ◽  
Z.Y. Luo ◽  
...  

ABSTRACTAn enhancement-mode GaN metal-insulator-semiconductor field-effect transistor was successfully fabricated on a GaN/AlGaN/GaN double heterojunction structure with SiO2 as insulator layer. The enhancement mode DC characteristics have been achieved in the device with a gate length of 6 μm and a gate width of 100 μm. The device exhibited a DC transconductance of 0.6 mS/mm and a maximum drain-source current of 5 mA/mm. The gate leakage current is lower than 10−6 A at a bias of -10 V and the gate breakdown voltage is higher than 20 V. The channel stands a good chance of forming by hole accumulation between the top GaN layer and the AlGaN layer. The p-channel can be attributed to the presence of a piezoelectric field in the heterojunction, and the strongly asymmetric band bending and carriers distribution induced by the piezoelectric field. High-frequency capacitance-voltage measurement also gives a circumstantial evidence of the presence of a p-channel in the device structure.


2001 ◽  
Vol 16 (12) ◽  
pp. 997-1001 ◽  
Author(s):  
Kun-Wei Lin ◽  
Chin-Chuan Cheng ◽  
Shiou-Ying Cheng ◽  
Kuo-Hui Yu ◽  
Chih-Kai Wang ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document