Low temperature wet-O2 annealing process for enhancement of inversion channel mobility and suppression of Vfb instability on 4H-SiC (0001) Si-face

Current power MOSFET devices on Silicon Carbide show a limited inversion channel mobility, which can be a result of the expected very high density of interface states near the conduction band . In the current work, the effect of the post implantation annealing temperature, the thermal oxidation and the nitrogen doping of the n-epi layer on the density of these interface traps is investigated using capacity-conductance measurements. Instead of the usage of very high frequencies as used in , in this investigation the measurements were performed in liquid nitrogen to decrease the recharging times of the interface traps.Due to the different processing the samples showed a wide spreading of the inversion channel mobility. The conductance measurements show a characteristic peak caused by the conduction band near interface traps especially for the low temperature measurements. But these traps could not be correlated to the mobility. Instead, a correlation to the nitrogen doping of the epi layer could be observed.

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Effect of Graphite Cap for Implant Activation on Inversion Channel Mobility in 4H-SiC MOSFETs

Materials Science Forum ◽

10.4028/www.scientific.net/msf.615-617.773 ◽

2009 ◽

Vol 615-617 ◽

pp. 773-776 ◽

Cited By ~ 15

Author(s):

Harsh Naik ◽

K. Tang ◽

T. Paul Chow

Keyword(s):

Low Temperature ◽

Carrier Concentration ◽

Threshold Voltage ◽

Hall Mobility ◽

Field Effect ◽

Gate Oxide ◽

Subthreshold Slope ◽

Field Effect Mobility ◽

Channel Mobility ◽

Inversion Channel

The effects of using a graphite capping layer during implant activation anneal on the performance of 4H-SiC MOSFETs has been evaluated. Two sets of samples, one with the graphite cap and another without, with a gate oxide process consisting of a low-temperature deposited oxide followed by NO anneal at 1175°C for 2hrs were used for characterization. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted for the two processes.

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SiC MOSFET Channel Mobility Dependence on Substrate Doping and Temperature Considering High Density of Interface Traps

Materials Science Forum ◽

10.4028/www.scientific.net/msf.556-557.835 ◽

2007 ◽

Vol 556-557 ◽

pp. 835-838 ◽

Cited By ~ 3

Author(s):

Amador Pérez-Tomás ◽

Michael R. Jennings ◽

Philip A. Mawby ◽

James A. Covington ◽

Phillippe Godignon ◽

...

Keyword(s):

Degradation Mechanism ◽

Mobility Model ◽

Effect Of Temperature ◽

Coulomb Scattering ◽

Interface Traps ◽

Channel Mobility ◽

Inversion Channel ◽

Scattering Effects ◽

Charge Concentration ◽

Substrate Doping

In prior work we have proposed a mobility model for describing the mobility degradation observed in SiC MOSFET devices, suitable for being implemented into a commercial simulator, including Coulomb scattering effects at interface traps. In this paper, the effect of temperature and doping on the channel mobility has been modelled. The computation results suggest that the Coulomb scattering at charged interface traps is the dominant degradation mechanism. Simulations also show that a temperature increase implies an improvement in field-effect mobility since the inversion channel concentration increases and the trapped charge is reduced due to bandgap narrowing. In contrast, increasing the substrate impurity concentration further degrades the fieldeffect mobility since the inversion charge concentration decreases for a given gate bias. We have good agreement between the computational results and experimental mobility measurements.

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Effects of Annealing Process on Crystallization and Low Temperature Resistance Properties of PP-R Composites

Journal of Wuhan University of Technology-Mater Sci Ed ◽

10.1007/s11595-018-1904-y ◽

2018 ◽

Vol 33 (4) ◽

pp. 855-862

Author(s):

Yulong Ma ◽

Xiaomeng Wang ◽

Wei Liu ◽

Wei Gong ◽

Li He

Keyword(s):

Low Temperature ◽

Annealing Process ◽

Temperature Resistance ◽

Low Temperature Resistance

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Excellent effects of hydrogen postoxidation annealing on inversion channel mobility of 4H-SiC MOSFET fabricated on (11 2 0) face

IEEE Electron Device Letters ◽

10.1109/55.974797 ◽

2002 ◽

Vol 23 (1) ◽

pp. 13-15 ◽

Cited By ~ 79

Author(s):

J. Senzaki ◽

K. Kojima ◽

S. Harada ◽

R. Kosugi ◽

S. Suzuki ◽

...

Keyword(s):

Channel Mobility ◽

Inversion Channel

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Inversion channel mobility and interface state density of diamond MOSFET using N-type body with various phosphorus concentrations

Applied Physics Letters ◽

10.1063/1.5100328 ◽

2019 ◽

Vol 114 (24) ◽

pp. 242101 ◽

Cited By ~ 6

Author(s):

Tsubasa Matsumoto ◽

Hiromitsu Kato ◽

Toshiharu Makino ◽

Masahiko Ogura ◽

Daisuke Takeuchi ◽

...

Keyword(s):

Interface State ◽

State Density ◽

Interface State Density ◽

Channel Mobility ◽

Inversion Channel

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High Threshold Voltage Normally off Ultra-Thin-Barrier GaN MISHEMT with MOCVD-Regrown Ohmics and Si-Rich LPCVD-SiNx Gate Insulator

Energies ◽

10.3390/en13102479 ◽

2020 ◽

Vol 13 (10) ◽

pp. 2479

Author(s):

Hsiang-Chun Wang ◽

Hsien-Chin Chiu ◽

Chong-Rong Huang ◽

Hsuan-Ling Kao ◽

Feng-Tso Chien

Keyword(s):

Threshold Voltage ◽

Gate Insulator ◽

High Threshold ◽

Potential Candidate ◽

Channel Mobility ◽

Switching Power ◽

Selective Area ◽

Inversion Channel ◽

Threshold Voltage Distribution ◽

Dimensional Electron Gas

A high threshold voltage (VTH) normally off GaN MISHEMTs with a uniform threshold voltage distribution (VTH = 4.25 ± 0.1 V at IDS = 1 μA/mm) were demonstrated by the selective area ohmic regrowth technique together with an Si-rich LPCVD-SiNx gate insulator. In the conventional GaN MOSFET structure, the carriers were induced by the inversion channel at a high positive gate voltage. However, this design sacrifices the channel mobility and reliability because a huge number of carriers are beneath the gate insulator directly during operation. In this study, a 3-nm ultra-thin Al0.25Ga0.75N barrier was adopted to provide a two-dimensional electron gas (2DEG) channel underneath the gate terminal and selective area MOCVD-regrowth layer to improve the ohmic contact resistivity. An Si-rich LPCVD-SiNx gate insulator was employed to absorb trace oxygen contamination on the GaN surface and to improve the insulator/GaN interface quality. Based on the breakdown voltage, current density, and dynamic RON measured results, the proposed LPCVD-MISHEMT provides a potential candidate solution for switching power electronics.

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Compatibility of POCl3 Gate Process with the Fabrication of Vertical 4H-SiC MOSFETs

Materials Science Forum ◽

10.4028/www.scientific.net/msf.1004.565 ◽

2020 ◽

Vol 1004 ◽

pp. 565-570

Author(s):

Tomokatsu Watanabe ◽

Munetaka Noguchi ◽

Shingo Tomohisa ◽

Naruhisa Miura

Keyword(s):

Thermal Treatment ◽

Low Temperature ◽

Negative Charge ◽

Charge Trapping ◽

Gate Oxide ◽

Device Fabrication ◽

Post Processing ◽

Production Lines ◽

Channel Mobility ◽

Device Operation

We used the POCl3 gate technique for the fabrication of 4H-SiC vertical MOSFETs, and examined its effect on the VTH-RON tradeoff and the compatibility with device fabrication. The gate oxide film was formed by thermal dry O2 oxidation followed by POCl3 or NO annealing. The POCl3 process reduced RON by about 30% compared with the NO process for the ones having VTH of 1.1 V, being attributed to the channel mobility enhancement. Moreover, the improvement was more effective for higher VTH designs. The conventional thermal treatment after the gate process considerably spoiled the channel mobility improvement brought by the POCl3 annealing and strengthened negative charge trapping in the gate oxide. The presumed extra-formed defects also affected the EOX dependence of tBD on the TDDB tests, being expected to shorten the gate oxide lifetime under practical device operation stress. Successful insertion of the POCl3 process into production lines depends upon careful low-temperature post processing.

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