scholarly journals High Threshold Voltage Normally off Ultra-Thin-Barrier GaN MISHEMT with MOCVD-Regrown Ohmics and Si-Rich LPCVD-SiNx Gate Insulator

Energies ◽  
2020 ◽  
Vol 13 (10) ◽  
pp. 2479
Author(s):  
Hsiang-Chun Wang ◽  
Hsien-Chin Chiu ◽  
Chong-Rong Huang ◽  
Hsuan-Ling Kao ◽  
Feng-Tso Chien

A high threshold voltage (VTH) normally off GaN MISHEMTs with a uniform threshold voltage distribution (VTH = 4.25 ± 0.1 V at IDS = 1 μA/mm) were demonstrated by the selective area ohmic regrowth technique together with an Si-rich LPCVD-SiNx gate insulator. In the conventional GaN MOSFET structure, the carriers were induced by the inversion channel at a high positive gate voltage. However, this design sacrifices the channel mobility and reliability because a huge number of carriers are beneath the gate insulator directly during operation. In this study, a 3-nm ultra-thin Al0.25Ga0.75N barrier was adopted to provide a two-dimensional electron gas (2DEG) channel underneath the gate terminal and selective area MOCVD-regrowth layer to improve the ohmic contact resistivity. An Si-rich LPCVD-SiNx gate insulator was employed to absorb trace oxygen contamination on the GaN surface and to improve the insulator/GaN interface quality. Based on the breakdown voltage, current density, and dynamic RON measured results, the proposed LPCVD-MISHEMT provides a potential candidate solution for switching power electronics.

2009 ◽  
Vol 615-617 ◽  
pp. 773-776 ◽  
Author(s):  
Harsh Naik ◽  
K. Tang ◽  
T. Paul Chow

The effects of using a graphite capping layer during implant activation anneal on the performance of 4H-SiC MOSFETs has been evaluated. Two sets of samples, one with the graphite cap and another without, with a gate oxide process consisting of a low-temperature deposited oxide followed by NO anneal at 1175°C for 2hrs were used for characterization. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted for the two processes.


2015 ◽  
Vol 821-823 ◽  
pp. 725-728
Author(s):  
Akio Shima ◽  
Kikuo Watanabe ◽  
Toshiyuki Mine ◽  
Naoki Tega ◽  
Hirotaka Hamamura ◽  
...  

We investigated the effect of an Al2O3 insertion layer in the gate insulator to make Vth higher and to improve the transconductance Gm in a SiC-MOSFET. Insertion of the Al2O3 layer successfully enlarged Vth by about 4 V. The Vth difference sub-threshold Id-Vg characteristics measured by sweeping the gate voltage bi-directionally indicates that insertion of the Al2O3 layer decreased the number of traps of electrons in the gate insulator. Due to this decrease, device reliability in long-term operation was improveed by smaller Vth shift in PBTI. It was also found that the insertion of the Al2O3 layer improved Gm by two times. Using this gate insulator, we succeeded in fabricating 600 V 20 A-class vertical SiC DMOSFETs with a high Vth (>5 V) and low Ron of 3 mΩcm2.


2017 ◽  
Vol 64 (4) ◽  
pp. 1554-1560 ◽  
Author(s):  
Liang He ◽  
Fan Yang ◽  
Liuan Li ◽  
Zijun Chen ◽  
Zhen Shen ◽  
...  

2014 ◽  
Vol 778-780 ◽  
pp. 985-988 ◽  
Author(s):  
Masayuki Furuhashi ◽  
Toshikazu Tanioka ◽  
Masayuki Imaizumi ◽  
Naruhisa Miura ◽  
Satoshi Yamakawa

We found that threshold voltage (Vth) of a 4H-SiC MOSFET increases drastically by performing low temperature wet oxidation after nitridation in a gate oxide process. The increment of Vth depends on the wet oxidation conditions. Wet oxidation increases the interface trap density (Dit) at deep level of SiC bandgap and decreases positive charge density inside the gate oxide layer. The amount change of the interface traps and the positive charges in the gate oxide makes Vth higher without a decrease in the channel mobility. We improved the trade-off between Vth and effective carrier mobility (μeff) in the MOSFET channel, and realized a low specific on-resistance (Ron,sp) SiC-MOSFET with Vth over 5 V by using the newly developed process.


2007 ◽  
Vol 556-557 ◽  
pp. 827-830 ◽  
Author(s):  
Keiko Fujihira ◽  
Naruhisa Miura ◽  
Tomokatsu Watanabe ◽  
Yukiyasu Nakao ◽  
Naoki Yutani ◽  
...  

Inversion-type 4H-SiC power MOSFETs using p-body implanted with retrograde profiles have been fabricated. The Al concentration at the p-body surface (Nas) is varied in the range from 5×1015 to 2×1018 cm-3. The MOSFETs show normally-off characteristics. While the Ron is 3 cm2 at Eox = (Vg-Vth)/dox ≅ 3 MV/cm for the MOSFET with the Nas of 2×1018 cm-3, the Ron is reduced by a decrease in the Nas and 26 mcm2 is attained for the device with the Nas of 5×1015 cm-3. The inversion channel mobility and threshold voltage are improved with a decrease in the Nas. By modifying the structural parameter of the MOSFET, a still smaller Ron of 7 mcm2 is achieved with a blocking voltage of 1.3 kV.


2010 ◽  
Vol 645-648 ◽  
pp. 479-482
Author(s):  
Aveek Chatterjee ◽  
Kevin Matocha ◽  
Vinayak Tilak ◽  
Jody Fronheiser ◽  
Hong Piao

We explain the role of nitrogen in simultaneously increasing the inversion channel mobility and reducing the threshold voltage of SiC MOSFET. A variety of computational techniques have been used to compute the atomic scale configuration of a nitridated SiC/SiO2 interface, and the corresponding change in Fermi level, inversion channel mobility, and threshold voltage. X-ray photoelectron spectroscopy (XPS) has been used to investigate the SiC/SiO2 interface to determine the nitrogen concentrations and chemical bonding. We elucidate the physics behind improved channel mobility due to NO anneal and demonstrate that the trade-off between threshold voltage and inversion channel mobility can be correlated to the extent of nitridation.


2017 ◽  
Vol 897 ◽  
pp. 497-500 ◽  
Author(s):  
Shinsuke Harada ◽  
Yusuke Kobayashi ◽  
A. Kinoshita ◽  
N. Ohse ◽  
Takahito Kojima ◽  
...  

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.


2007 ◽  
Vol 556-557 ◽  
pp. 835-838 ◽  
Author(s):  
Amador Pérez-Tomás ◽  
Michael R. Jennings ◽  
Philip A. Mawby ◽  
James A. Covington ◽  
Phillippe Godignon ◽  
...  

In prior work we have proposed a mobility model for describing the mobility degradation observed in SiC MOSFET devices, suitable for being implemented into a commercial simulator, including Coulomb scattering effects at interface traps. In this paper, the effect of temperature and doping on the channel mobility has been modelled. The computation results suggest that the Coulomb scattering at charged interface traps is the dominant degradation mechanism. Simulations also show that a temperature increase implies an improvement in field-effect mobility since the inversion channel concentration increases and the trapped charge is reduced due to bandgap narrowing. In contrast, increasing the substrate impurity concentration further degrades the fieldeffect mobility since the inversion charge concentration decreases for a given gate bias. We have good agreement between the computational results and experimental mobility measurements.


2010 ◽  
Vol 46 (18) ◽  
pp. 1280 ◽  
Author(s):  
C.-T. Chang ◽  
T.-H. Hsu ◽  
E.Y. Chang ◽  
Y.-C. Chen ◽  
H.-D. Trinh ◽  
...  

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