scholarly journals Inversion channel mobility and interface state density of diamond MOSFET using N-type body with various phosphorus concentrations

2019 ◽  
Vol 114 (24) ◽  
pp. 242101 ◽  
Author(s):  
Tsubasa Matsumoto ◽  
Hiromitsu Kato ◽  
Toshiharu Makino ◽  
Masahiko Ogura ◽  
Daisuke Takeuchi ◽  
...  
2012 ◽  
Vol 717-720 ◽  
pp. 709-712 ◽  
Author(s):  
Shuji Katakami ◽  
Manabu Arai ◽  
Kensuke Takenaka ◽  
Yoshiyuki Yonezawa ◽  
Hitoshi Ishimori ◽  
...  

We investigated the effect of post-oxidation annealing in wet O2 and N2O ambient, following dry O2 oxidation on the SiC MOS interfacial properties by using p-type MOS capacitors. The interfacial properties were dramatically improved by the introduction of hydrogen or nitrogen atoms into the SiO2/SiC interface, in each POA process. Notably, the N2O-POA process at 1200 °C or higher reduced the interface state density more effectively than the wet-O2-POA process, and offers a promising method to further improve the inversion channel mobility of p-channel SiC MOS devices.


2000 ◽  
Vol 622 ◽  
Author(s):  
G.Y. Chung ◽  
C.C. Tin ◽  
J. R. Williams ◽  
K. McDonald ◽  
M. Di Ventra ◽  
...  

ABSTRACTResults are reported for the passivation of interface states near the conduction band edge in n-4H-SiC using post-oxidation anneals in nitric oxide, ammonia and forming gas (N2/5%H2). Anneals in nitric oxide and ammonia reduce the interface state density significantly, while forming gas anneals are largely ineffective. Results suggest that interface states in SiO2/SiC and SiO2/Si have different origins, and a model is described for interface state passivation by nitrogen in the SiO2/SiC system. The inversion channel mobility of 4H-SiC MOSFETs increases with the NO annealing.


2010 ◽  
Vol 1246 ◽  
Author(s):  
Dai Okamoto ◽  
Hiroshi Yano ◽  
Shinya Kotake ◽  
Kenji Hirata ◽  
Tomoaki Hatayama ◽  
...  

AbstractWe propose a new technique to fabricate 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) with high inversion channel mobility. P atoms were incorporated into the SiO2/4H-SiC(0001) interface by post-oxidation annealing using phosphoryl chloride (POCl3). The interface state density at 0.2 eV from the conduction band edge was reduced to less than 1 × 1011 cm−2eV−1 by the POCl3 annealing at 1000 °C. The peak field-effect mobility of 4H-SiC MOSFETs on (0001) Si-face processed with POCl3 annealing at 1000 °C was approximately 90 cm2/Vs. The high channel mobility is attributed to the reduced interface state density near the conduction band edge.


2006 ◽  
Vol 527-529 ◽  
pp. 1043-1046 ◽  
Author(s):  
Kenji Fukuda ◽  
Makoto Kato ◽  
Shinsuke Harada ◽  
Kazutoshi Kojima

SiC power MOSFETs are expected to be normally-off type fast switching devices. The on-resistance of SiC power MOSFETs is much higher than the value predicted from the physical properties of SiC. This is caused by the low channel mobility due to high interface state density (Dit). We have already reported that 4H-SiC MOSFETs on the C(0001 _ ) face had higher inversion-channel mobility. However, there is the SiO2/SiC interface roughness problem in SiC MOSFETs. There are many steps at the SiO2/SiC interface because a high off-angle is necessary for SiC epitaxial growth. These steps might make SiO2/SiC interfaces rough, which leads to reduction of channel mobility. In this work, we have investigated the effect of the SiO2/SiC interface roughness caused by the off-angle on the inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(0001 _ ) face. The inversion-channel mobility of MOSFETs fabricated on the 4H-SiC C(0001 _ ) face substrate with the vicinal off-angle(0.8°) is higher than that of MOSFETs fabricated on the 4H-SiC C(0001 _ ) face substrate with the 8° off-angle. Reduction of the off-angle is very useful for improvement of channel mobility. A C(0001 _ ) epitaxial substrate with the vicinal off-angle would be suitable for SiC DMOSFETs.


2011 ◽  
Vol 276 ◽  
pp. 87-93
Author(s):  
Y.Y. Gomeniuk ◽  
Y.V. Gomeniuk ◽  
A. Nazarov ◽  
P.K. Hurley ◽  
Karim Cherkaoui ◽  
...  

The paper presents the results of electrical characterization of MOS capacitors and SOI MOSFETs with novel high-κ LaLuO3 dielectric as a gate oxide. The energy distribution of interface state density at LaLuO3/Si interface is presented and typical maxima of 1.2×1011 eV–1cm–2 was found at about 0.25 eV from the silicon valence band. The output and transfer characteristics of the n- and p-MOSFET (channel length and width were 1 µm and 50 µm, respectively) are presented. The front channel mobility appeared to be 126 cm2V–1s–1 and 70 cm2V–1s–1 for n- and p-MOSFET, respectively. The front channel threshold voltages as well as the density of states at the back interface are presented.


2017 ◽  
Vol 897 ◽  
pp. 115-118
Author(s):  
Martin Domeij ◽  
Jimmy Franchi ◽  
Krister Gumaelius ◽  
K. Lee ◽  
Fredrik Allerstam

Lateral implanted SiC MOSFETs and NMOS capacitors were fabricated and used to extract channel mobility and interface state density DIT for three different gate oxides. DIT values were extracted using the high(1 MHz)-low(1 kHz) method for NMOS capacitors and the subthreshold slope for MOSFETs. The subthreshold slope extraction gave 6-20 times higher DIT values compared to the high-low method, presumably because the high-low method cannot capture the fastest traps [1]. None of the methods resulted in clear proportionality between the inverse channel mobility and DIT. The subthreshold slope gave similar DIT values for samples with different surface p-doping concentrations indicating that the method is not sensitive to the threshold voltage.


2008 ◽  
Vol 600-603 ◽  
pp. 679-682 ◽  
Author(s):  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto

Deposited SiN/SiO2 stack gate structures have been investigated to improve the 4H-SiC MOS interface quality. Capacitance-voltage measurements on fabricated SiN/SiO2 stack gate MIS capacitors have indicated that the interface state density is reduced by post-deposition annealing in N2O at 1300°C. The usage of thin SiN and increase in N2O-annealing time lead to a low interface state density of 1×1011 cm-2eV-1 at EC – 0.2 eV. Oxidation of the SiN during N2O annealing has resulted in improvement of SiC MIS interface. The fabricated SiN/SiO2 stack gate MISFETs demonstrate a high channel mobility of 32 cm2/Vs on (0001)Si face and 40 cm2/Vs on (000-1)C face.


2009 ◽  
Vol 615-617 ◽  
pp. 789-792
Author(s):  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto

P-channel MOSFETs have been fabricated on 4H-SiC (0001) face as well as on 4H-SiC (03-38) and (11-20) faces. The gate oxides were formed by thermal oxidation in dry N2O ambient, which is widely accepted to improve the performance of n-channel SiC MOSFETs. The p-channel SiC MOSFETs with N2O-grown oxides on 4H-SiC (0001), (03-38), and (11-20) faces show a channel mobility of 7 cm2/Vs, 11 cm2/Vs, and 17 cm2/Vs, respectively. From the quasi-static C-V curves measured by using gate-controlled diodes, the interface state density was calculated by an original method. The interface state density was the lowest at the SiO2/4H-SiC (03-38) interface (about 1x1012 cm-2eV-1 at EV + 0.2 eV). The authors have applied deposited oxides to the 4H-SiC p-channel MOSFETs. The (0001), (03-38), and (11-20) MOSFETs with deposited oxides exhibit a channel mobility of 10 cm2/Vs, 13 cm2/Vs, and 17 cm2/Vs, respectively. The deposited oxides are one of effective approaches to improve both n-channel and p-channel 4H-SiC MOS devices.


2000 ◽  
Vol 640 ◽  
Author(s):  
Hiroyuki Matsunami ◽  
Tsunenobu Kimoto ◽  
Hiroshi Yano

ABSTRACTHigh-quality 4H-SiC has been epitaxially grown on (1120) substrates by chemical vapor deposition. The physical properties of epilayers and MOS interfaces on both (1120) and off-axis (0001) substrates are elucidated. An unintentionally doped 4H-SiC epilayer on (1120) shows a donor concentration of 1×1014 cm−3 with a total trap concentration as low as 3.8×1012 cm−3. Inversion-type planar MOSFETs fabricated on 4H-SiC (1120) exhibit a high channel mobility of 96 cm2/Vs. The channel mobility decreases according to the T−2.2 dependence above 200K, indicating reduced Coulomb scattering and/or electron trapping. The superior MOS interface on (1120) originates from the much lower interface state density near the conduction band edge.


2014 ◽  
Vol 778-780 ◽  
pp. 418-423 ◽  
Author(s):  
Hironori Yoshioka ◽  
Takashi Nakamura ◽  
Junji Senzaki ◽  
Atsushi Shimozato ◽  
Yasunori Tanaka ◽  
...  

We focused on the inability of the common high-low method to detect very fast interface states, and developed methods to evaluate such states (CψS method). We have investigated correlation between the interface state density (DIT) evaluated by the CψS method and MOSFET performance, and found that the DIT(CψS) was well reflected in MOSFET performance. Very fast interface states which are generated by nitridation restricted the improvement of subthreshold slope and field-effect mobility.


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