A Charge-Trap Memory Device with a Composition-Modulated Zr-Silicate High-
                    k
                    Dielectric Multilayer Structure

A synaptic device that contains weight information between two neurons is one of the essential components in a neuromorphic system, which needs highly linear and symmetric characteristics of weight update. In this study, a charge trap flash (CTF) memory device with a multilayered high-κ barrier oxide structure on the MoS2 channel is proposed. The fabricated device was oxide-engineered on the barrier oxide layers to achieve improved synaptic functions. A comparison study between two fabricated devices with different barrier oxide materials (Al2O3 and SiO2) suggests that a high-κ barrier oxide structure improves the synaptic operations by demonstrating the increased on/off ratio and symmetry of synaptic weight updates due to a better coupling ratio. Lastly, the fabricated device has demonstrated reliable potentiation and depression behaviors and spike-timing-dependent plasticity (STDP) for use in a spiking neural network (SNN) neuromorphic system.

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Synthesis and Electrical Characterization of a MOS Memory Containing Pt Nanoparticles Deposited at a SiO2/ HfO2 Interface

MRS Proceedings ◽

10.1557/proc-830-d6.4 ◽

2004 ◽

Vol 830 ◽

Cited By ~ 1

Author(s):

Ch. Sargentis ◽

K. Giannakopoulos ◽

A. Travlos ◽

D. Tsamakis

Keyword(s):

High Frequency ◽

Semiconductor Nanocrystals ◽

Electrical Characterization ◽

Pt Nanoparticles ◽

Memory Device ◽

Memory Devices ◽

High K ◽

High K Dielectric ◽

Mos Device

ABSTRACTMOS memory devices containing semiconductor nanocrystals have drawn considerable attention recently, due to their advantages when compared to the conventional memories. Only little work has been done on memory devices containing metal nanoparticles.We describe the fabrication of a novel MOS device with embedded Pt nanoparticles in the HfO2 / SiO2 interface of a MOS device. Using as control oxide, a high-k dielectric, our device has a great degree of scalability. The fabricated nanoparticles are very small (about 5 nm) and have high density. High frequency C-V measurements demonstrate that this device operates as a memory device.

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Trap Assisted Conduction in High K Dielectric Capacitors on 4H-SiC

Materials Science Forum ◽

10.4028/www.scientific.net/msf.556-557.679 ◽

2007 ◽

Vol 556-557 ◽

pp. 679-682 ◽

Cited By ~ 3

Author(s):

Ming Hung Weng ◽

Rajat Mahapatra ◽

Alton B. Horsfall ◽

Nicolas G. Wright ◽

Paul G. Coleman ◽

...

Keyword(s):

Barrier Height ◽

Conduction Mechanism ◽

Electrical Measurements ◽

Temperature Dependent ◽

Conduction Model ◽

High K ◽

Current Conduction ◽

Capacitor Structure ◽

High K Dielectric ◽

A Charge

The characteristic of trap assisted conduction and interface states for a Pd/TiO2/SiO2/SiC structure has been investigated at temperatures up to 500 °C. Thermally oxidized Ti/SiO2 gate capacitors fabricated by dry oxidation in O2 were studied. The electrical measurements show the current conduction through this capacitor structure is controlled by a trap assisted conduction mechanism at low bias and the barrier height (φA) between the metal and the TiO2 was extracted. The current density in the dielectric stacks is also shown to be strongly temperature dependent. The results demonstrate that the formation of a charge dipole under the Pd contact is responsible for barrier height and not any changes in the behaviour of the TiO2 film itself, such as a change in concentration of trapping centres. The reported results indicate electron trapping property across the SiO2 layer is consistent with fitting experimental results to the trap assisted conduction model.

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