Cubic-Structured HfLaO for the Blocking Layer of a Charge-Trap Type Flash Memory Device

2010 ◽  
Vol 3 (9) ◽  
pp. 091501 ◽  
Author(s):  
Jong Kyung Park ◽  
Youngmin Park ◽  
Myeong Ho Song ◽  
Sung Kyu Lim ◽  
Jae Sub Oh ◽  
...  
2010 ◽  
Vol 96 (22) ◽  
pp. 222902 ◽  
Author(s):  
Jong Kyung Park ◽  
Youngmin Park ◽  
Sung Kyu Lim ◽  
Jae Sub Oh ◽  
Moon Sig Joo ◽  
...  

2011 ◽  
Vol 58 (2) ◽  
pp. 288-295 ◽  
Author(s):  
Seongjae Cho ◽  
Won Bo Shim ◽  
Yoon Kim ◽  
Jang-Gn Yun ◽  
Jong Duk Lee ◽  
...  

Author(s):  
Eui Joong Shin ◽  
Sung Won Shin ◽  
Seung Hwan Lee ◽  
Tae In Lee ◽  
Min Ju Kim ◽  
...  

Crystals ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 70
Author(s):  
Minkyung Kim ◽  
Eunpyo Park ◽  
In Soo Kim ◽  
Jongkil Park ◽  
Jaewook Kim ◽  
...  

A synaptic device that contains weight information between two neurons is one of the essential components in a neuromorphic system, which needs highly linear and symmetric characteristics of weight update. In this study, a charge trap flash (CTF) memory device with a multilayered high-κ barrier oxide structure on the MoS2 channel is proposed. The fabricated device was oxide-engineered on the barrier oxide layers to achieve improved synaptic functions. A comparison study between two fabricated devices with different barrier oxide materials (Al2O3 and SiO2) suggests that a high-κ barrier oxide structure improves the synaptic operations by demonstrating the increased on/off ratio and symmetry of synaptic weight updates due to a better coupling ratio. Lastly, the fabricated device has demonstrated reliable potentiation and depression behaviors and spike-timing-dependent plasticity (STDP) for use in a spiking neural network (SNN) neuromorphic system.


2016 ◽  
Vol 2016 ◽  
pp. 1-6 ◽  
Author(s):  
W. J. Liu ◽  
L. Chen ◽  
P. Zhou ◽  
Q. Q. Sun ◽  
H. L. Lu ◽  
...  

We demonstrated a flash memory device with chemical-vapor-deposited graphene as a charge trapping layer. It was found that the average RMS roughness of block oxide on graphene storage layer can be significantly reduced from 5.9 nm to 0.5 nm by inserting a seed metal layer, which was verified by AFM measurements. The memory window is 5.6 V for a dual sweep of ±12 V at room temperature. Moreover, a reduced hysteresis at the low temperature was observed, indicative of water molecules or −OH groups between graphene and dielectric playing an important role in memory windows.


2008 ◽  
Vol 11 (9) ◽  
pp. H252 ◽  
Author(s):  
Jing Pu ◽  
Sun-Jung Kim ◽  
Young-Sun Kim ◽  
Byung Jin Cho

2017 ◽  
Vol 111 (3) ◽  
pp. 033501 ◽  
Author(s):  
Yu-Heng Liu ◽  
Cheng-Min Jiang ◽  
Hsiao-Yi Lin ◽  
Tahui Wang ◽  
Wen-Jer Tsai ◽  
...  

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