scholarly journals Ambipolar Current Suppression, Analog/RF and Linearity Performance Improvement of Dual Material Stacked Gate Oxide TFET with Dielectric Pocket

Author(s):  
dharmender nishad ◽  
kaushal Nigam

Abstract In this article, the impact of high-K and low-K dielectric pockets on DC, analog/RF, and linearity performance parameters of dual material stacked gate oxide-dielectric pocket-tunnel field-effect transistor (DMSGO-DP-TFET) is investigated. In this regard, a stacked gate oxide (SiO2 + HfO2) with workfunction engineering is taken into consideration to improve the ON-state current (ION ), and suppress the ambipolar current (Iamb). To further improve the performance of the device, a high-K dielectric pocket (HfO2) is used at the drain-channel interface to suppress the Iamb, and at the source-channel interface a low-K dielectric pocket is used to improve the ION and analog/RF performance. Moreover, length of stacked gate segments (L1, L2, L3), pocket height, and thickness are optimized to attain better ION /IOFF ratio, and suppress the Iamb which helps to achieve higher gain and design of analog/RF circuits. The DMSGO-DP-TFET outperforms the dual material control gate-dielectric pocket-TFET (DMCG-DP-TFET) with SiO2 gate oxide and shows increment in ION /IOFF (∼ 4.23 times), 84 % increment in transconductance (gm), 136 % increment in cut-off frequency (fT ), 126 % increment in gain-bandwidth-product (GBP), and better linearity performance parametrs such as gm2 ,gm3, VIP2, VIP3 and IIP3 making the proposed device useful for low power and radio frequency applications.

2021 ◽  
Author(s):  
Dharmender Kumar ◽  
Kaushal Nigam

Abstract This paper investigates the impact of lowK and high-K dielectric pockets on DC characteristics, analog/RF, and linearity performance of dual material stack gate oxide-tunnel field-effect transistor (DMSGODP-TFET). For this, a stack gate oxide with workfunction is considered to enhance the ON-state current (ION ), lower ambipolar current (Iamb) and lower the subthreshold swing. For this case, the gate electrode is tri-segmented, named as tunnel gate (M1), control gate (M2) and auxiliary gate (M3) with different gate lengths (L1, L2, L3) and work functions (φ1, φ2, φ3), respectively. To maintain dual-work functionality, the possible combinations of these work functions are considered. Technology computer-aided design (TCAD) simulations are performed and noted that the workfunction combination (φ1 = φ3 < φ2) outperforms as compared to other combinations. Where φ1 on the source side is used to enhance the ION , while φ3 (equal to φ1) is used on the drain side to minimize the Iamb. To further enhance the device performance, a high-K dielectric pocket is considered at the drain junction to suppress the Iamb whereas, a low-K dielectric pocket is employed at the source junction to enhance the ION . Moreover, length of gate segments, dielectric pocket height, and thickness are optimized to achieve a better switching ratio, subthreshold swing (SS) and reduce the Iamb which helps in the gain of device and design of analog/RF circuits. The proposed device as compared to dual material control gate-dielectric pocket-TFET (DMCG-DP-TFET) with SiO2 gate oxide shows improvement in ION /IOF F (∼ 4.23 times), 84 % increase in transconductance (gm), 136 % increase in cut-off frequency (fT ), 126 % increase in gain bandwidth product (GBP), point subthreshold swing (15.8 mV/decade) and other significant improvements in linearity figure of merits (FOMs) making the proposed device useful for low power switching, analog/RF and linearity applications.


2021 ◽  
Author(s):  
SHIKHA U S ◽  
Rekha K James ◽  
Jobymol Jacob ◽  
Anju Pradeep

Abstract The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.


2008 ◽  
Vol 57 (6) ◽  
pp. 3807
Author(s):  
Luan Su-Zhen ◽  
Liu Hong-Xia ◽  
Jia Ren-Xu ◽  
Cai Nai-Qiong

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