scholarly journals Synthesis of a terminal device of a multiplex data exchange channel to FPGA

2021 ◽  
Vol 2052 (1) ◽  
pp. 012056
Author(s):  
V I Zharkov ◽  
M N Petrov ◽  
I Y Griskevich
Keyword(s):  
Data Exchange ◽  
Description Language ◽  
Software Environment ◽  
Pass Filter ◽  
Serial Interface ◽  
Operating Modes ◽  
Terminal Device ◽  
Hardware Description ◽  
High Pass ◽  
Transmission Speed

Abstract The article presents a technology for developing a terminal device for a multiplexed serial interface for data exchange to FPGA. The development was carried out using the System Verilog hardware description language. To meet demanding requirements. presented to this interface in terms of transmission speed, as well as the duration of transmitted and received bits of information, the device includes a built-in signal duration analyzer, which can also be used to exclude the influence of a part of the impulse noise that “leaked” through the input high-pass filter. The presented device has passed the verification of the main operating modes in the ModelSim-Altera software environment.

The Design of Digital Filter Based on DSP Builder

2014 ◽  
Vol 602-605 ◽  
pp. 2641-2644
Author(s):  
Xiao Li Hu ◽  
Li Ding ◽  
Zhi Gang Zhang
Keyword(s):  
Digital Filter ◽  
Hardware Description Language ◽  
Description Language ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Paper Model ◽  
Dsp Builder ◽  
Quartus Ii ◽  
Low Pass ◽  
Hardware Description

This paper model digital FIR low-pass by using the Toolbox of the DSP Builder in MATLAB and convert to VHDL hardware description language, compile and simulation through QUARTUS II software automatically, download and verified by EPF10K20RC208-4.The design combine MATLAB software with FPGA hardware organic ally and completes the transplant of the FIR low-pass filter.

A V-Band Two Pole High-Pass Filter for Frequency Quadrupler Design

2016 ◽  
Vol 6 (1) ◽  
pp. 56
Author(s):  
Maryam Abata ◽  
Mahmoud Mehdi ◽  
Said Mazer ◽  
Moulhime El Bekkali ◽  
Catherine Algani
Keyword(s):  
Pass Filter ◽  
High Pass Filter ◽  
V Band ◽  
High Pass

Baseline-free sensor fault detection for piezoelectric array

2021 ◽  
pp. 1045389X2110188
Author(s):  
Qibo Mao ◽  
Yuande Wang ◽  
Shizuo Huang
Keyword(s):  
Prior Knowledge ◽  
Frequency Response Function ◽  
Sensor Array ◽  
Piezoelectric Element ◽  
Piezoelectric Sensor ◽  
Steel Beam ◽  
Sensor Fault ◽  
Pass Filter ◽  
Sensor Fault Detection ◽  
High Pass

In this study, a new methodology is presented to detect the sensor fault for piezoelectric array based on the filtered frequency response function (FRF) shapes. The proposed method does not require prior knowledge about healthy piezoelectric array. First, the imaginary parts of FRFs from the piezoelectric array during vibration are measured and normalized to obtain the FRF shapes in different frequencies. Then the irregularities in these FRF shapes are extracted by using high-pass filter with properly chosen cut-off frequency. These abnormal irregularities on the filtered FRF shape curves indicate the location of the faulty sensor, due to the irregularity of FRF shapes introduced by the faulty piezoelectric element. The proposed sensor fault method is experimentally demonstrated on a clamped-clamped steel beam mounted with piezoelectric buzzer array. Two common piezoelectric sensor fault types including sensor breakage and debonding are evaluated. The experimental results indicate that the proposed method has great potential in the detection of the sensor fault for piezoelectric array as it is simple and does not require the FRF data of the healthy sensor array as a baseline.

scholarly journals High-Bandpass Filters in Electrocardiography: Source of Error in the Interpretation of the ST Segment

2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
F. Buendía-Fuentes ◽  
M. A. Arnau-Vives ◽  
A. Arnau-Vives ◽  
Y. Jiménez-Jiménez ◽  
J. Rueda-Soriano ◽  
...  
Keyword(s):  
Real Time ◽  
Fourier Transforms ◽  
Pass Filter ◽  
Discrete Fourier Transforms ◽  
Real Time Mode ◽  
Asymptomatic Patients ◽  
St Segment ◽  
Coronary Syndromes ◽  
Clinically Significant ◽  
High Pass

Introduction. Artifactual variations in the ST segment may lead to confusion with acute coronary syndromes. Objective. To evaluate how the technical characteristics of the recording mode may distort the ST segment. Material and Method. We made a series of electrocardiograms using different filter configurations in 45 asymptomatic patients. A spectral analysis of the electrocardiograms was made by discrete Fourier transforms, and an accurate recomposition of the ECG signal was obtained from the addition of successive harmonics. Digital high-pass filters of 0.05 and 0.5 Hz were used, and the resulting shapes were compared with the originals. Results. In 42 patients (93%) clinically significant alterations in ST segment level were detected. These changes were only seen in “real time mode” with high-pass filter of 0.5 Hz. Conclusions. Interpretation of the ST segment in “real time mode” should only be carried out using high-pass filters of 0.05 Hz.

Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM

2014 ◽  
Vol 573 ◽  
pp. 176-180
Author(s):  
G. Kavitha ◽  
B. Kirthiga ◽  
N. Kirubanandasarathy
Keyword(s):  
Low Power ◽  
Orthogonal Frequency Division Multiplexing ◽  
Ofdm System ◽  
Description Language ◽  
Fft Processor ◽  
Synthesis Tool ◽  
Mimo Ofdm ◽  
Hardware Description ◽  
Fft Algorithms ◽  
Area Efficient

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.

Hierarchical Configurable Petri Net Modeling in VHDL

2012 ◽  
Vol 58 (4) ◽  
pp. 397-402 ◽  
Author(s):  
Michał Doligalski ◽  
Marian Adamski
Keyword(s):  
Petri Nets ◽  
Petri Net ◽  
Control Process ◽  
Discrete Control ◽  
Dual Model ◽  
Description Language ◽  
Direct Support ◽  
Hardware Description ◽  
Logical Synthesis ◽  
State Machine Diagram

Abstract The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dual model is an alternative way for behavioral description of the discrete control process. Dual model consists of two correlated models: UML state machine diagram and hierarchical configurable Petri net (HCfgPN). HCfgPN are Petri nets variant with direct support of exceptions handling mechanism. Logical synthesis of dual model is realized by the description of HCfgPN model by means of hardware description language. The paper presents placesoriented method for HCfgPN description in VHDL language

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