scholarly journals A comprehensive study of current-crowding effect in high power vertical AlInGaN LEDs under high pulsed current

2021 ◽  
Vol 2086 (1) ◽  
pp. 012084
Author(s):  
A E Ivanov ◽  
A V Aladov ◽  
N Atalnishnikh ◽  
A E Chernyakov ◽  
A L Zakgeim

Abstract The goal of the study is examination of current-crowding effect in high power AlInGaN LEDs. This effect was presented by mapping of EL (electroluminescence) near filed under high pulse current. LED chip of vertical design was study in high range of current (10−9 ÷ 70A). This operating mode of LEDs are interesting for different applications, such as pumping lasers, VLC and LiFi, as well as for investigation accelerated degradation process of LEDs.

2021 ◽  
Author(s):  
Paul O. Leisher ◽  
Michelle Labrecque ◽  
Kevin McClune ◽  
Elliot Burke ◽  
Daniel Renner ◽  
...  

Author(s):  
R. B. Swertfeger ◽  
S. K. Patra ◽  
R. J. Deri ◽  
M. C. Boisselle ◽  
D. L. Pope ◽  
...  

1996 ◽  
Vol 421 ◽  
Author(s):  
M. Osiński ◽  
D. L. Barton ◽  
C. J. Helms ◽  
P. Perlin ◽  
N. H. Berg ◽  
...  

AbstractThe reliability of devices fabricated in GaN and related alloys, especially under high current densities as would be found in lasers, has yet to be fully characterized. Our previous work [1] investigated the degradation of GaN-based blue light emitting diodes (LEDs) under high pulsed current stress. This work indicated a possible correlation between the high crystal defect density and failures caused by metal migration along these defect tubes. To assess the impact of this data on devices under more normal conditions, several LEDs from both older and more recent production lots were placed in a controlled temperature and current environment for several thousand hours. The test started with a constant 20 mA current for the first 1000 hours and continued for another 1650 hours at various currents up to 70 mA, all at a temperature of 23 °C. During this test, one of the older generation LED's output degraded by more than 50%. Subsequent failure analysis showed that this was caused by a crack which isolated part of the active region from the p-contact. The remaining LEDs were returned to life testing where the temperature was subsequently increased by 5 °C after each 500 hours of testing. The output from one of the newer LEDs dreiven at 70 mA degraded to 55% of its original value after 3600 hours and a second newer LED degraded by a similar amount after 4400 hours. The first failure, LED #16, did not exhibit a significant change in its I-V characteristics indicating that a change in the package transparency was a likely cause for the observed degradation. The second failure, LED #17, did show a noticeable change in its I-V characteristics. This device was subsequently returned to life testing where the degradation process will be monitored for further changes.


2013 ◽  
Vol 583 ◽  
pp. 41-44 ◽  
Author(s):  
Razvan Ionescu ◽  
Mihai Mardare ◽  
Aurel Dorobantu ◽  
Stefan Vermesan ◽  
Elena Marinescu ◽  
...  

Metallic implants for ostheosynthesis are used for temporary replacement of the the original functions and to accelerate the bone consolidation after fracture. Stainless steel is frequently used for bone fracture fixation in spite of its sensitivity to corrosion in aggressive environments such as human body 1. This study is focused on the effect of associated use of various metallic implants for osteosynthesis and the occurrence of local adverse reactions as a tissue response. Once the degradation process occurs metal ions are released and are held responsible for these undesirable effects. This was the main motivation of starting a comprehensive study which involved the clinical data of patients who underwent such surgery, analysis of tissues around the implants and also investigation of metallic explants through microscopy techniques.


2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.


Author(s):  
Paul Leisher ◽  
Michelle Labrecque ◽  
Elliot Burke ◽  
Kevin McClune ◽  
Daniel Renner ◽  
...  

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