A 25 Gbps VCSEL driving ASIC: an attempt for ultra-high-speed front-end readout applications

2022 ◽  
Vol 17 (01) ◽  
pp. C01040
Author(s):  
C. Zhao ◽  
D. Guo ◽  
Q. Chen ◽  
N. Fang ◽  
Y. Gan ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Test Results ◽  
Eye Diagram ◽  
Optical Links ◽  
Optical Module ◽  
Active Feedback ◽  
High Bandwidth ◽  
Output Driver ◽  
Very High

Abstract This paper presents the design and the test results of a 25 Gbps VCSEL driving ASIC fabricated in a 55 nm CMOS technology as an attempt for the future very high-speed optical links. The VCSEL driving ASIC is composed of an input equalizer stage, a pre-driver stage and a novel output driver stage. To achieve high bandwidth, the pre-driver stage combines the inductor-shared peaking structure and the active-feedback technique. A novel output driver stage uses the pseudo differential CML driver structure and the adjustable FFE pre-emphasis technique to improve the bandwidth. This VCSEL driver has been integrated in a customized optical module with a VCSEL array. Both the electrical function and optical performance have been fully evaluated. The output optical eye diagram has passed the eye mask test at the data rate of 25 Gbps. The peak-to-peak jitter of 25 Gbps optical eye is 19.5 ps and the RMS jitter is 2.9 ps.

Very high-speed ROM using bipolar/CMOS technology

1988 ◽  
Vol 71 (7) ◽  
pp. 18-26 ◽  
Author(s):  
Koozaburoo Kurita ◽  
Takasi Hotta ◽  
Masahiro Ueno ◽  
Atsuo Hotta
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Very High

IMPLEMENTATION ISSUES FOR HIGH-BANDWIDTH FIELD-PROGRAMMABLE ANALOG ARRAYS

1998 ◽  
Vol 08 (05n06) ◽  
pp. 541-558 ◽  
Author(s):  
VINCENT C. GAUDET ◽  
P. GLENN GULAK
Keyword(s):  
Cmos Technology ◽  
Current Conveyor ◽  
Test Results ◽  
Programmable Analog ◽  
Field Programmable ◽  
High Bandwidth ◽  
Field Programmable Analog Arrays ◽  
Analog Arrays ◽  
A Current ◽  
Field Programmable Analog Array

This paper is a tutorial introduction to field-programmable analog arrays, as well as a review of existing field-programmable analog array architectures, of both educational and industrial origin. Circuit issues relevant to the development of high-bandwidth FPAAs are presented. A current conveyor-based architecture, which promises to achieve video bandwidths, is described. Test results are presented for the CMOS current conveyor-based FPAA building block, with programmable transconductors and capacitors. Measurements indicate bandwidths in excess of 10 MHz, and functionality of amplifiers, integrators, differentiators, and adders. The die area is 1.5 mm× 3.5 mm in a 0.8 μm CMOS technology.

scholarly journals A survey on advanced transmission technologies for high bandwidth and good signal quality for high-speed railways

2021 ◽  
Vol 23 (1) ◽  
pp. 293
Author(s):  
Abdul Rafay ◽  
Sevia Mahdaliza Idrus ◽  
Kamaludin Mohamad Yusof ◽  
Siti Hasunah Mohammad
Keyword(s):  
High Speed ◽  
Multiple Input Multiple Output ◽  
Satellite Networks ◽  
Signal Quality ◽  
High Penetration ◽  
Multiple Input ◽  
Input Multiple Output ◽  
High Bandwidth ◽  
Good Signal ◽  
Very High

Ahigh-speedrailway (HSR) has gained very high popularity for passengersdue to the fast, reliable, economical and convenient during traveling a verylong-distance journey. Thedemandfor advancedbroadbandservices such aswatching4K movies, cloud computing andonline gaming, has exponentiallyincreased fortravelerson thehigh-speedtrain(HST).The HSTcan’t providegood bandwidth to facilitate these services for travelers via existingtechnologies such as cellular networksand satellite networks because offrequent handoffs, high penetration and fading.So, the bandwidth degradesdramatically due to these issues. Research workers have developed proposalsto handle these problems by advanced transmission technologies for HSR.Until now,varioustransmissionschemeshave beensuggestedby researchworks with thefocusfor either high bandwidth or signal qualityimprovement. This paper presents a survey on advanced transmissiontechnologies for high bandwidth and good signal quality. In this paper, acomprehensive survey of the appropriate literature published that concentrateon advanced transmission methods in HSR communications in getting higherbandwidth efficiency and maximize the signal quality is presented. Advancedtransmission method can be categorized into orthogonal frequencydivisionmultiplexing (OFDM), multiple-input multiple-output (MIMO) and radio-over-fiber (RoF).

scholarly journals CMOS Inverter as Analog Circuit: An Overview

2019 ◽  
Vol 9 (3) ◽  
pp. 26 ◽  
Author(s):  
Woorham Bae
Keyword(s):  
Analog Circuits ◽  
High Speed ◽  
Analog Circuit ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Cmos Inverter ◽  
Technology Scaling ◽  
Resistive Feedback ◽  
Output Driver

Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper.

LDLA14: a 14 Gbps optical transceiver ASIC in 55 nm for NICA multi purpose detector project

2022 ◽  
Vol 17 (01) ◽  
pp. C01027
Author(s):  
Q. Chen ◽  
D. Guo ◽  
C. Zhao ◽  
R. Arteche ◽  
C. Ceballos ◽  
...  
Keyword(s):  
Single Channel ◽  
Cmos Technology ◽  
Capacitive Coupling ◽  
Cavity Surface ◽  
Eye Diagram ◽  
Limiting Amplifier ◽  
Novel Structure ◽  
Vertical Cavity Surface ◽  
Surface Emitting Laser ◽  
Output Driver

Abstract This paper presents the design and test results of a 14 Gbps optical transceiver ASIC (LDLA14) fabricated in a 55 nm CMOS technology for NICA Multi Purpose Detector (MPD) project. The LDLA14 is a single-channel bidirectional (1Tx + 1Rx) optical transceiver ASIC, including a Laser Driver (LD) module and a Limiting Amplifier (LA) module. It would drive the Vertical Cavity Surface Emitting Laser (VCSEL) of Transmitter Optical Sub-Assembly (TOSA) and receive signals from Photo Diode (PD) of Receiver Optical Sub-Assembly (ROSA), respectively. In the LDLA14, a novel structure of capacitive coupling pre-emphasis is proposed in the output driver of LD to obtain peaking effect without sacrifice the modulation current swing. A shared inductor technology and a Continuous Time Linear Equalizer (CTLE) pre-emphasis structure are added in the output buffer of LA to improve the quality of the output eye diagram. The dimension of LDLA14 is 1.5 mm × 1.3 mm, and the power consumption is 178 mW. The Peak-to-Peak Jitter (PPJ) and Root-Mean-Square Jitter (RMSJ) of the 14 Gbps optical eye diagram of LD in the Tx direction are 22.5 ps and 3.5 ps, respectively. The PPJ and RMSJ of the 14 Gbps electrical eye diagram of LA in the Rx direction are 23.1 ps and 4.7 ps, respectively. The BER tests have been conducted in Tx, Rx directions and the Tx-Rx loop condition, and the BER less than 10−12 is achieved in all tests.

Design of a 10 Gbps VCSEL Current Driver in Active Feedback Technology

2012 ◽  
Vol 588-589 ◽  
pp. 868-871 ◽  
Author(s):  
Jin Fei Wang ◽  
Ying Mei Chen ◽  
Ling Tian ◽  
Li Zhang
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Cavity Surface ◽  
Output Stage ◽  
Active Feedback ◽  
Vertical Cavity Surface ◽  
Chip Size ◽  
Surface Emitting Laser ◽  
Circuit Technique ◽  
Vertical Cavity

A design of 10 Gbps Vertical Cavity Surface Emitting Laser (VCSEL) driver using 0.18µm CMOS technology is presented in this paper. The core unit of the driver consists of pre-amplify stage and output stage circuit. Technique of three stages differential amplifier with low impedance load and active feedback are employed in pre-amplify stage, and technique of C3A is adopted in output stage to get low power consume and high speed. The simulation results show that the circuit can work at the speed rate of 10 Gbps and maximum of 13 Gbps with a 1.8V power supply. The output modulation current is up to 12.5mA and the power dissipation is 77mW. The chip size is 0.45mm  0.47mm.

CMOS realisation of analogue processor for early vision processing

2011 ◽  
Vol 59 (2) ◽  
pp. 141-147 ◽  
Author(s):  
W. Jendernalik ◽  
J. Jakusz ◽  
G. Blakiewicz ◽  
R. Piotrowski ◽  
S. Szczepański
Keyword(s):  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Proof Of Concept ◽  
Early Vision ◽  
Vision Chip ◽  
Vision Processing ◽  
Real Time Image ◽  
Time Image ◽  
Very High

CMOS realisation of analogue processor for early vision processing The architecture concept of a high-speed low-power analogue vision chip, which performs low-level real-time image algorithms is presented. The proof-of-concept prototype vision chip containing 32 × 32 photosensor array and 32 analogue processors is fabricated using a 0.35 μm CMOS technology. The prototype can be configured to register and process images with very high speed, reaching 2000 frames per second, or achieve very low power consumption, several μW. Finally, the experimental results are presented and discussed.

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