Oxide-thickness determination in thin-insulator MOS structures

1988 ◽  
Vol 35 (4) ◽  
pp. 432-438 ◽  
Author(s):  
B. Ricco ◽  
P. Olivo ◽  
T.N. Nguyen ◽  
T.-S. Kuan ◽  
G. Ferriani
1999 ◽  
Vol 595 ◽  
Author(s):  
W.P. Li ◽  
R. Zhang ◽  
J. Yin ◽  
X.H. Liu ◽  
Y.G. Zhou ◽  
...  

AbstractGaN-based metal-ferroelectric-semiconductor (MFS) structure has been fabricated by using ferroelectric Pb(Zr0.53Ti0.47)O3 (PZT) instead of conventional oxides as gate insulators. The GaN and PZT films in the MFS structures have been characterized by various methods such as photoluminescence (PL), wide-angle X-ray diffraction (XRD) and high-resolution X-ray diffraction (HRXRD). The Electric properties of GaN MFS structure with different oxide thickness have been characterized by high-frequency C-V measurement. When the PZT films are as thick as 1 µm, the GaN active layers can approach inversion under the bias of 15V, which can not be observed in the traditional GaN MOS structures. When the PZT films are about 100 nm, the MFS structures can approach inversion just under 5V. All the marked improvements of C-V behaviors in GaN MFS structures are mainly attributed to the high dielectric constant and large polarization of the ferroelectric gate oxide.


2006 ◽  
Vol 527-529 ◽  
pp. 987-990 ◽  
Author(s):  
Tsunenobu Kimoto ◽  
H. Kawano ◽  
Masato Noborio ◽  
Jun Suda ◽  
Hiroyuki Matsunami

Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.


2000 ◽  
Vol 13 (2) ◽  
pp. 152-158 ◽  
Author(s):  
G. Ghibaudo ◽  
S. Bruyere ◽  
T. Devoivre ◽  
B. DeSalvo ◽  
E. Vincent

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