Improvement of oxide thickness determination on MOS structures using capacitance–voltage measurements at high frequencies

2001 ◽  
Vol 4 (1-3) ◽  
pp. 163-166 ◽  
Author(s):  
L. Soliman ◽  
E. Duval ◽  
M. Benzohra ◽  
E. Lheurette ◽  
K. Ketata ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
High Frequencies ◽  
Thickness Determination ◽  
Capacitance Voltage ◽  
Mos Structures

Effects of Arsenic Segregation and Electron Trapping on the Capacitance-Voltage Behavior of Polysilicon and Polycide Gates

1990 ◽  
Vol 182 ◽  
Author(s):  
J. Lin ◽  
S. Batra ◽  
K. Park ◽  
J. Lee ◽  
S. Banerjee ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Electron Trapping ◽  
Dopant Segregation ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Capacitance Voltage ◽  
Higher Temperature ◽  
Amorphous Si ◽  
Mos Structures ◽  
Mos Device

AbstractThis paper discusses the effects of dopant segregation and electron trapping on the capacitance-voltage characteristics of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi2 layer. The effects of gate bias, annealing temperature, silicide formation and polysilicon grain microstructure on the C-V characteristics have also been studied. The results show that insufficient arsenic redistribution at 800°C, coupled with carrier trapping at polysilicon grain boundaries and dopant segregation in TiSi2 causes depletion effects in the polysilicon gate and in turn, an anomalous capacitance-voltage behavior. The depletion tends to increase the “effective” gate oxide thickness and thereby degrade MOS device performance. Higher temperature anneals (≥ 900°C) are sufficient to achieve degenerate doping in the polysilicon gates and avoid the depletion effects.

Oxide-thickness determination in thin-insulator MOS structures

1988 ◽  
Vol 35 (4) ◽  
pp. 432-438 ◽  
Author(s):  
B. Ricco ◽  
P. Olivo ◽  
T.N. Nguyen ◽  
T.-S. Kuan ◽  
G. Ferriani
Keyword(s):  
Oxide Thickness ◽  
Thickness Determination ◽  
Mos Structures

scholarly journals Study of Interface Charge Densities for ZrO2and HfO2Based Metal-Oxide-Semiconductor Devices

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
N. P. Maity ◽  
Reshmi Maity ◽  
R. K. Thapa ◽  
S. Baishya
Keyword(s):  
Metal Oxide ◽  
Oxide Thickness ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Charge Densities ◽  
Interface Charge ◽  
Capacitance Voltage ◽  
P Type ◽  
Mos Structures ◽  
Good Agreement

A thickness-dependent interfacial distribution of oxide charges for thin metal oxide semiconductor (MOS) structures using high-kmaterials ZrO2and HfO2has been methodically investigated. The interface charge densities are analyzed using capacitance-voltage (C-V) method and also conductance (G-V) method. It indicates that, by reducing the effective oxide thickness (EOT), the interface charge densities (Dit) increases linearly. For the same EOT,Dithas been found for the materials to be of the order of 1012 cm−2 eV−1and it is originated to be in good agreement with published fabrication results at p-type doping level of1×1017 cm−3. Numerical calculations and solutions are performed by MATLAB and device simulation is done by ATLAS.

Radiation Hardness for Silicon Oxide and Aluminum Oxide on 4H-SiC

2018 ◽  
Vol 924 ◽  
pp. 229-232 ◽  
Author(s):  
Anders Hallén ◽  
Sethu Saveda Suvanam
Keyword(s):  
Proton Irradiation ◽  
Silicon Oxide ◽  
Positive Charge ◽  
Gate Dielectric ◽  
Radiation Hardness ◽  
Flat Band ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Radiation Hard ◽  
Mos Structures

The radiation hardness of two dielectrics, SiO2and Al2O3, deposited on low doped, n-type 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

FABRICATION AND ELECTRICAL PROPERTIES OF Au/PVDF-TrFE/LaZrOx/Si(100) STRUCTURE

2010 ◽  
Vol 24 (22) ◽  
pp. 4203-4208 ◽  
Author(s):  
HUI-SEONG HAN ◽  
GWANG-GEUN LEE ◽  
BYUNG-EUN PARK
Keyword(s):  
Thin Films ◽  
Polyvinylidene Fluoride ◽  
Oxide Thickness ◽  
Voltage Sweep ◽  
Window Width ◽  
Capacitance Voltage ◽  
Coating Method ◽  
Insulator Layers ◽  
Lanthanum Zirconium Oxide ◽  
P Type

Metal-ferroelectric-insulator-semiconductor structure capacitors with a polyvinylidene fluoride trifluoroethylene (75/25) (PVDF-TrFE) ferroelectric and a lanthanum zirconium oxide ( LaZrO x) insulator layers were fabricated on a p-type Si(100) substrate in this work. The thin films were prepared using the spin-coating method. The LaZrO x thin films were crystallized at 750°C for 30 min in an O 2 ambient. Negligible hysteresis was observed from the C–V (capacitance-voltage) characteristic of the LaZrO x/ Si structure. The equivalent oxide thickness (EOT) was about 8.2 nm. Then the PVDF-TrFE film was spin-coated on the LaZrO x/ Si structure. To crystallize the PVDF-TrFE, the structure was annealed at 165°C for 30 min. The memory window width in the C–V curve of the Au/PVDF - TrFE/LaZrO x/ Si structure was about 4 V for a voltage sweep of ±5 V, and the leakage current density was about 10-8 A/cm 2 at 35 kV/cm for a 100-nm-thick film.

Deep depletion capacitance–voltage technique for spatial distribution of traps across the substrate in MOS structures

2020 ◽  
Vol 173 ◽  
pp. 107905
Author(s):  
Han Bin Yoo ◽  
Jintae Yu ◽  
Haesung Kim ◽  
Ji Hee Ryu ◽  
Sung-Jin Choi ◽  
...  
Keyword(s):  
Spatial Distribution ◽  
Capacitance Voltage ◽  
Mos Structures
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