Measurement of buried oxide thermal conductivity for accurate electrothermal simulation of SOI device

AbstractThe impact of two implant parameters, namely the implant substrate temperature and implant beam current, on the physical and electrical properties of SIMOX buried oxide are investigated. Three implant substrate temperatures, 540 °C, 590 °C, and 640 °C and three beam current, 45 mA, 55 mA, 65 mA, are investigated. Results from thermal conductivity and surface photovoltage measurements show no apparent differences between samples. Results from interface roughness shows a decreasing trend as the substrate temperature and beam current increases. For the samples with different implant temperatures, the high‐field conduction shows an opposite dependence for top‐interface versus substrate injection. This behavior can be explained by the conservation of silicon in the buried oxide. Correlation of surface photovoltage and high‐field conduction shows weak positive dependency while that of interface roughness and high‐field conduction shows dependency only when the sets of temperature variation and beam current variation are decoupled.

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Synthesis and Thermal Conductivity Measurement of High-Integrity Ultrathin Oxygen-Implanted Buried Oxide Layers

Japanese Journal of Applied Physics ◽

10.1143/jjap.43.2185 ◽

2004 ◽

Vol 43 (4B) ◽

pp. 2185-2187

Author(s):

Yemin Dong ◽

Jing Chen ◽

Meng Chen ◽

Xi Wang ◽

Ping He ◽

...

Keyword(s):

Thermal Conductivity ◽

Conductivity Measurement ◽

Thermal Conductivity Measurement ◽

Oxide Layers ◽

Buried Oxide ◽

High Integrity

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Thermal Conductivity of SOI LDMOS Device

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.571.8 ◽

2012 ◽

Vol 571 ◽

pp. 8-12

Author(s):

Yan Xiong ◽

Yu Shu Lai

Keyword(s):

Thermal Conductivity ◽

Characteristic Curve ◽

Lower Surface ◽

Negative Resistance ◽

The Self ◽

Oxide Semiconductor ◽

Heating Effect ◽

Field Plate ◽

Self Heating ◽

Buried Oxide

In this paper, the thermal conductivity of lateral double diffused metal oxide semiconductor (LDMOS) was studied. In order to optimize their properties, the LDMOS device based on the lower surface of field (RESURF) theory join the second field plate technology. Power device self-heating effect will affect the carrier mobility, making its negative resistance effect in IV characteristic curve under the high-power condition. As the thermal conductivity of SiO2 is low, the self-heating effect of SOI device is more obvious. The simulation using Silvaco -TCAD software for different buried oxide (BOX) with different SOI layer thickness accordingly show that the thicker SOI layer and the thinner buried oxide layer, the smaller the self-heating effect.

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Behavior of contact-silicided TFSOI gate structures

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100172036 ◽

1994 ◽

Vol 52 ◽

pp. 860-861

Author(s):

N. David Theodore ◽

Juergen Foerstner ◽

Peter Fejes

Keyword(s):

Semiconductor Device ◽

Series Resistance ◽

Field Effect Transistors ◽

Silicon Layer ◽

Device Fabrication ◽

Silicon On Insulator ◽

Continuous Layer ◽

Buried Oxide ◽

Device Structures ◽

Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

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