Crosstalk noise minimization in domino logic design

2001 ◽  
Vol 20 (9) ◽  
pp. 1091-1100 ◽  
Author(s):  
Ki-Wook Kim ◽  
Sung-Mo Kang
Keyword(s):  
Logic Design ◽  
Crosstalk Noise ◽  
Domino Logic

Pseudo Dual Supply Voltage Domino Logic Design

2005 ◽  
Vol 1 (2) ◽  
pp. 145-152 ◽  
Author(s):  
Abdulkadir U. Diril ◽  
Yuvraj S. Dhillon ◽  
Abhijit Chatterjee ◽  
Adit D. Singh
Keyword(s):  
Supply Voltage ◽  
Logic Design ◽  
Domino Logic

High-Speed Domino Logic Design

2006 ◽  
Author(s):  
S.K. Sahari ◽  
C.P. Tiong ◽  
N. Rajaee ◽  
R. Sapawi
Keyword(s):  
High Speed ◽  
Logic Design ◽  
Domino Logic

scholarly journals Clock Delayed Dual Keeper Domino-Logic Design with Reduced Switching

2019 ◽  
Vol 9 (1S3) ◽  
pp. 397-402
Keyword(s):  
Power Consumption ◽  
Logic Design ◽  
Output Node ◽  
Domino Logic ◽  
Technology Node ◽  
Switching Mechanism ◽  
Speed Performance ◽  
Domino Circuit ◽  
Simulation Results ◽  
Logic Unit

Clock Delayed Dual Keeper domino logic style with Static Switching mechanism (CDDK_SS) using delayed enabling of the keeper circuit and modified discharge path has been proposed in this paper. In CDDK domino circuit, the principle of delayed enabling of keeper circuit offers reduced contention between keeper circuit and Pull Down Network (PDN). The modified discharge path at the output node eradicates the switching at the output node for identical TRUE inputs during the pre-charge phase. This facilitates in obtaining static like output in contrast with conventional domino logic. The simulation results of Arithmetic and Logic Unit (ALU) subsystems demonstrate 17.7% reduction in dynamic power consumption while compared to conventional domino logic. Furthermore, 62% enhancement in speed performance has been achieved with good robustness. Design and simulation have been executed using Cadence® Virtuoso, with UMC 90nm technology node library.

DOMINO LOGIC SYNTHESIS SYSTEM AND ITS APPLICATIONS

2006 ◽  
Vol 15 (02) ◽  
pp. 277-287 ◽  
Author(s):  
KO YOSHIKAWA ◽  
SHIGETO INUI ◽  
YASUHIKO HAGIHARA ◽  
YUICHI NAKAMURA ◽  
TAKESHI YOSHIMURA
Keyword(s):  
Bin Packing ◽  
New Technology ◽  
Logic Synthesis ◽  
Logic Circuits ◽  
Logic Design ◽  
Technology Mapping ◽  
Synthesis System ◽  
Domino Logic ◽  
Mapping Algorithms ◽  
Mapping Algorithm

We have developed a domino logic synthesis system with a new technology mapping algorithm based on a bin packing algorithm that reduces the levels of the circuits and considers the complexity of domino primitive cells. Domino logic circuits have 20–50% performance advantage over static circuits. By using this system, designing domino logic circuits becomes much easier than manual design. The primary reason is that logic design is completely automated by the system. The second reason is that domino primitive cell layout is simplified by our new technology mapping algorithms that considers the complexity of domino primitive cells.

Digital Logic Design

2009 ◽  
Author(s):  
Guy Even ◽  
Moti Medina
Keyword(s):  
Digital Logic ◽  
Logic Design
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