Pseudo Dual Supply Voltage Domino Logic Design

2005 ◽  
Vol 1 (2) ◽  
pp. 145-152 ◽  
Author(s):  
Abdulkadir U. Diril ◽  
Yuvraj S. Dhillon ◽  
Abhijit Chatterjee ◽  
Adit D. Singh
Keyword(s):  
Supply Voltage ◽  
Logic Design ◽  
Domino Logic

A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology

2019 ◽  
Vol 28 (10) ◽  
pp. 1950165 ◽  
Author(s):  
Sandeep Garg ◽  
Tarun K. Gupta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Power Reduction ◽  
Maximum Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Maximum Delay

In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[Formula: see text]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[Formula: see text] higher compared to different existing techniques in FinFET SG mode and is 1.42–[Formula: see text] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [Formula: see text] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.

High-Speed Domino Logic Design

2006 ◽  
Author(s):  
S.K. Sahari ◽  
C.P. Tiong ◽  
N. Rajaee ◽  
R. Sapawi
Keyword(s):  
High Speed ◽  
Logic Design ◽  
Domino Logic

scholarly journals Clock Delayed Dual Keeper Domino-Logic Design with Reduced Switching

2019 ◽  
Vol 9 (1S3) ◽  
pp. 397-402
Keyword(s):  
Power Consumption ◽  
Logic Design ◽  
Output Node ◽  
Domino Logic ◽  
Technology Node ◽  
Switching Mechanism ◽  
Speed Performance ◽  
Domino Circuit ◽  
Simulation Results ◽  
Logic Unit

Clock Delayed Dual Keeper domino logic style with Static Switching mechanism (CDDK_SS) using delayed enabling of the keeper circuit and modified discharge path has been proposed in this paper. In CDDK domino circuit, the principle of delayed enabling of keeper circuit offers reduced contention between keeper circuit and Pull Down Network (PDN). The modified discharge path at the output node eradicates the switching at the output node for identical TRUE inputs during the pre-charge phase. This facilitates in obtaining static like output in contrast with conventional domino logic. The simulation results of Arithmetic and Logic Unit (ALU) subsystems demonstrate 17.7% reduction in dynamic power consumption while compared to conventional domino logic. Furthermore, 62% enhancement in speed performance has been achieved with good robustness. Design and simulation have been executed using Cadence® Virtuoso, with UMC 90nm technology node library.

DOMINO LOGIC SYNTHESIS SYSTEM AND ITS APPLICATIONS

2006 ◽  
Vol 15 (02) ◽  
pp. 277-287 ◽  
Author(s):  
KO YOSHIKAWA ◽  
SHIGETO INUI ◽  
YASUHIKO HAGIHARA ◽  
YUICHI NAKAMURA ◽  
TAKESHI YOSHIMURA
Keyword(s):  
Bin Packing ◽  
New Technology ◽  
Logic Synthesis ◽  
Logic Circuits ◽  
Logic Design ◽  
Technology Mapping ◽  
Synthesis System ◽  
Domino Logic ◽  
Mapping Algorithms ◽  
Mapping Algorithm

We have developed a domino logic synthesis system with a new technology mapping algorithm based on a bin packing algorithm that reduces the levels of the circuits and considers the complexity of domino primitive cells. Domino logic circuits have 20–50% performance advantage over static circuits. By using this system, designing domino logic circuits becomes much easier than manual design. The primary reason is that logic design is completely automated by the system. The second reason is that domino primitive cell layout is simplified by our new technology mapping algorithms that considers the complexity of domino primitive cells.

scholarly journals Heterogeneous Logic: a High Performance and Low Power Non-CMOS 4-1 Multiplexer

2020 ◽  
Vol 9 (3) ◽  
pp. 3237-3243
Keyword(s):  
Power Dissipation ◽  
High Performance ◽  
Simulation Analysis ◽  
Supply Voltage ◽  
State Of The Art ◽  
Average Power ◽  
Logic Design ◽  
Logic Function ◽  
Second Stage ◽  
Pass Transistor

A novel non-CMOS 4-1 multiplexer using heterogeneous logic style is presented in this brief. The heterogeneous logic design uses the combination of three basic logic styles such as Dual Value Logic (DVL), Transmission Gate Logic (TGL) and Simple Pass Transistor Logic (SPTL). The design uses only two stacking transistors in between the supply rails. Only 16 transistors are required for the actual logic function in the proposed state-of-the-art design. Number of transistors is reduced by distinctly choosing DVL and TGL in the first stage as per the input combination. Later stage of the multiplexer is constructed using SPTL. A required logic style is chosen at first and second stage in accordance with input bit combination to minimize the number of transistors, enhance the speed of logic transition and reduce the average power dissipation. The design and simulation analysis of proposed circuit is carried out at 22nm technology using Pyxis Schematic and Pyxis Simulator. Comparison of wide-ranging simulated results of proposed design, CMOS tree multiplexer and CMOS NOR multiplexer at various supply voltages and frequencies on same technology node manifests that the performance of proposed heterogeneous multiplexer is better in terms of speed and power dissipation. At minimum possible supply voltage of 0.8V and at moderate frequency of 1GHz, the proposed multiplexer achieves, reduced power dissipation of 17.3% and reduced in delay of 9.14%. The count of transistors including inverters is also less compared to CMOS tree type and CMOS NOR type multiplexers. However, robustness of mixed logic style designs is to be improved compared to CMOS designs.

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