Gated Clock and Revised Keeper (GCRK) Domino Logic Design in 16 nm CMOS Technology

2021 ◽  
pp. 1-8
Author(s):  
Smita Singhal ◽  
Anu Mehra
Keyword(s):  
Cmos Technology ◽  
Logic Design ◽  
Domino Logic ◽  
Gated Clock

scholarly journals Domino Sense Analogous Contradict Planning of A CMOS

2019 ◽  
Vol 8 (6S2) ◽  
pp. 261-264
Keyword(s):  
Cmos Technology ◽  
Vlsi Circuits ◽  
Domino Logic ◽  
Flip Flop ◽  
Cell Library ◽  
Dynamic Circuits ◽  
Wide Range ◽  
Pipeline Segment

The fundamental target of this paper comprises of the domino rationale way and checking path. A fast wide range parallel contradicts that accomplishes high working frequencies throughout an account pipeline segment demeanor utilizing just three undemanding redundant CMOS-rationale module types. The three essential module types are isolated by D flip failure. The three element types are set in an exceedingly dull constitution in the tallying way and Domino Logic way. Enthusiastic domino rationale circuits are broadly utilized in present day computerized VLSI circuits. These dynamic circuits are utilized in superior structures. Along these lines simultaneously refreshing the tally state with a consistent deferral at all tallying way module regarding the clock edge. This construction is versatile to self-assertive portion counter widths utilizing just the three module types. The deferral counter is contained the underlying module admittance times only, three-info AND-entryway delay and a D-type flip-flop. The motivation behind the project is to diminish the Power utilization and CMOS Technology in the counter way and Domino rationale way by utilizing DSCH in Microwind Tool. The proposed Counter way is structured utilizing 0.10µm TSMC Digital cell library and its expended 0.215mW.

A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology

2019 ◽  
Vol 28 (10) ◽  
pp. 1950165 ◽  
Author(s):  
Sandeep Garg ◽  
Tarun K. Gupta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Power Reduction ◽  
Maximum Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Maximum Delay

In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[Formula: see text]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[Formula: see text] higher compared to different existing techniques in FinFET SG mode and is 1.42–[Formula: see text] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [Formula: see text] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.

scholarly journals Editor’s Column

2019 ◽  
Vol 23 (2) ◽  
Author(s):  
Mladen Knezic
Keyword(s):  
Signal Processing ◽  
Power Dissipation ◽  
Audio Signal ◽  
Cmos Technology ◽  
Power Grids ◽  
Audio Signal Processing ◽  
Domino Logic ◽  
December Issue ◽  
Simulation Results ◽  
And Control

THE December issue of Electronics journal in 2019 contains five regular papers that present recent advancements in the field of electronics, audio signal processing and control theory applied to power grids balancing. The paper “A Novel Domino Logic with Modified Keeper in 16nm CMOS Technology”, authored by S. Singhal, A. Mehra, and U. Tripathi, proposes a novel domino logic aimed at improving the power dissipation and reducing consumed area of the circuit. A comparison with previous techniques is provided in the paper as well as simulation results obtained using Ngspice simulator.

Pseudo Dual Supply Voltage Domino Logic Design

2005 ◽  
Vol 1 (2) ◽  
pp. 145-152 ◽  
Author(s):  
Abdulkadir U. Diril ◽  
Yuvraj S. Dhillon ◽  
Abhijit Chatterjee ◽  
Adit D. Singh
Keyword(s):  
Supply Voltage ◽  
Logic Design ◽  
Domino Logic

Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD

2017 ◽  
Vol 27 (03) ◽  
pp. 1850046 ◽  
Author(s):  
Sadulla Shaik ◽  
K. Sri Rama Krishna ◽  
Ramesh Vaddi
Keyword(s):  
Energy Efficiency ◽  
Energy Efficient ◽  
Low Voltage ◽  
Field Effect Transistors ◽  
Full Adder ◽  
Cmos Technology ◽  
Logic Design ◽  
Transmission Gate ◽  
Reliability Characteristics ◽  
Efficient Option

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20[Formula: see text]nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET’s steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has [Formula: see text]91% smaller energy delay product (EDP) and [Formula: see text]84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2[Formula: see text]V VDD.

High-Speed Domino Logic Design

2006 ◽  
Author(s):  
S.K. Sahari ◽  
C.P. Tiong ◽  
N. Rajaee ◽  
R. Sapawi
Keyword(s):  
High Speed ◽  
Logic Design ◽  
Domino Logic
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