Estimation of threshold voltage shift in a-IGZO TFTs under different bias temperature stress by improved stretched-exponential equation

We report a 1700V, 5.5mΩ-cm24H-SiC DMOSFET capable of 225°C operation. The specific on-resistance of the DMOSFET designed for 1200V applications is 8.8mΩ-cm2at 225°C, an increase of only 60% compared to the room temperature value. The low specific on-resistance at high temperatures enables a smaller die size for high temperature operation. Under a negative gate bias temperature stress (BTS) at VGS=-15 V at 225°C for 20 minutes, the devices show a threshold voltage shift of ΔVTH=-0.25 V demonstrating one of the key device reliability requirements for high temperature operation.

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Threshold Voltage Instabilities of Present SiC-Power MOSFETs under Positive Bias Temperature Stress

Materials Science Forum ◽

10.4028/www.scientific.net/msf.858.481 ◽

2016 ◽

Vol 858 ◽

pp. 481-484 ◽

Cited By ~ 12

Author(s):

Gerald Rescher ◽

Gregor Pobegen ◽

Tibor Grasser

Keyword(s):

Temperature Stress ◽

Threshold Voltage ◽

Physical Property ◽

Oxide Thickness ◽

Positive Bias ◽

Threshold Voltage Shift ◽

Power Mosfets ◽

Fundamental Physical Property ◽

Bias Temperature Stress ◽

Silicon Based

We study the threshold voltage (Vth) instability of commercially available silicon carbide (SiC) power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress (PBTS). A positive bias near the Vth causes a threshold voltage shift of 0.7 mV per decade in time per nanometer oxide thickness in the temperature range between-50 °C and 150 °C. Recovery at +5 V after a 100 s +25 V gate-pulse causes a recovery between-1.5 mV/dec/nm and-1.0 mV/dec/nm at room temperature and is decreasing with temperature. All devices show similar stress, recovery and temperature dependent behavior indicating that the observed Vth instabilities are likely a fundamental physical property of the SiC-SiO2 system caused by electron trapping in near interface traps. It is important to note that the trapping is not causing permanent damage to the interface like H-bond-breakage in silicon based devices and is nearly fully reversible via a negative gate bias.

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Modeling of stretched-exponential and stretched-hyperbola time dependence of threshold voltage shift in thin-film transistors

Journal of Applied Physics ◽

10.1063/1.4917209 ◽

2015 ◽

Vol 117 (14) ◽

pp. 144501 ◽

Cited By ~ 5

Author(s):

Taeho Jung

Keyword(s):

Thin Film ◽

Time Dependence ◽

Threshold Voltage ◽

Thin Film Transistors ◽

Threshold Voltage Shift ◽

Voltage Shift ◽

Stretched Exponential

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Impact of Nitric Oxide Post Oxidation Anneal on the Bias Temperature Instability and the On-Resistance of 4H-SiC nMOSFETs

Materials Science Forum ◽

10.4028/www.scientific.net/msf.821-823.709 ◽

2015 ◽

Vol 821-823 ◽

pp. 709-712 ◽

Cited By ~ 1

Author(s):

Gerald Rescher ◽

Gregor Pobegen ◽

Thomas Aichinger

Keyword(s):

Nitric Oxide ◽

Electric Field ◽

Temperature Stress ◽

Threshold Voltage ◽

Positive Bias ◽

Threshold Voltage Shift ◽

Bias Temperature Instability ◽

Bias Temperature Stress ◽

The Impact ◽

Stress Voltage

We study the impact of different nitric oxide (NO) post oxidation annealing (POA) procedures on the on resistance Ron of n-channel MOSFETs and on the threshold voltage shift ∆Vth following positive bias temperature stress (PBTS). All samples were annealed in an NO containing atmosphere at various temperatures and times. A positive stress voltage of 30 V was chosen which corresponds to an electric field of about 4.3 MV/cm. The NO POA causes a decrease in overall ∆Vth for longer NO POA times and higher NO POA temperatures. As opposed to the change in ∆Vth, the device Ron increases with NO POA temperature and time.

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