Asymmetric etching profile control during high aspect ratio Plasma etch

2018 ◽  
Author(s):  
Zusing Yang ◽  
Li-Ian Wu ◽  
Sheng-Yuan Chang ◽  
Yuan-Chieh Chiu ◽  
Hong-Ji Lee ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
Plasma Etch ◽  
Profile Control ◽  
Etching Profile

Prediction of Abnormal Etching Profile in High-Aspect-Ratio Via/Hole Etching Using On-Wafer Monitoring System

2010 ◽  
Vol 49 (4) ◽  
pp. 04DB14 ◽  
Author(s):  
Hiroto Ohtake ◽  
Seiichi Fukuda ◽  
Butsurin Jinnai ◽  
Tomohiko Tatsumi ◽  
Seiji Samukawa
Keyword(s):  
Aspect Ratio ◽  
Monitoring System ◽  
High Aspect Ratio ◽  
Etching Profile ◽  
Via Hole

scholarly journals Etch profile control of high-aspect ratio deep submicrometer α-Si gate etch

2001 ◽  
Vol 14 (3) ◽  
pp. 242-254 ◽  
Author(s):  
Hyun-Mog Park ◽  
D.S. Grimard ◽  
J.W. Grizzle ◽  
F.L. Terry
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
Profile Control ◽  
Deep Submicrometer ◽  
Etch Profile

A Two-Step Spacer Etch for High-Aspect-Ratio Gate Stack Process

2000 ◽  
Vol 611 ◽  
Author(s):  
Chien Yu ◽  
Rich Wise ◽  
Anthony Domenicucci
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
Gate Stack ◽  
Methyl Fluoride ◽  
Thermal Oxide ◽  
Profile Control ◽  
The Stability ◽  
Better Than

ABSTRACTA highly selective nitride etch was developed for gate stack spacer process in advanced memory programs. Based on methyl fluoride chemistry with better than 8:1 selectivity of nitride:oxide, this process exhibits minimal erosion to the underlying RTO thermal oxide for consistent diffusion ion-implant control. As the groundrule changed to 0.175um and below, a two-step etch scheme was employed to maintain the profile control in high-aspect-ratio structures. The stability and repeatability of the process is demonstrated in the SPC chart of the post etch FTA site measurement.

Deep Reactive Ion Etched Submicron Beam/Trench Characterization

2001 ◽  
Author(s):  
Gary O’Brien ◽  
Xing Cheng ◽  
L. J. Guo
Keyword(s):  
Standard Deviation ◽  
Aspect Ratio ◽  
High Aspect Ratio ◽  
Nanoimprint Lithography ◽  
Silicon Substrates ◽  
Plasma Etch ◽  
Depth Variation ◽  
Technology Systems

Abstract Sub-micron width high aspect ratio beam/trench arrays are etched into silicon substrates using a Surface Technology Systems (STS) deep reactive ion etch (RIE) tool equipped with a time multiplexed plasma etch/passivation cycle scheme. The oxide mask is patterned by nanoimprint lithography and minimizes lateral trench etching by adjusting the significant etch parameters. High aspect ratio trench arrays 350nm wide with a 700nm period are etched to a depth of 10 μm with typical sidewall asperities on the order of 30nm. A dual etch process is used to reduce scalloping near the trench surface using HBr/Cl to etch the initial 500nm followed by the STS process using C4F8/SF6 chemistry. The dual etch process resulted in a reduction of sidewall asperities from 75nm to less than 25nm. In addition, the dual etch process reduced the trench array depth variation from a measured standard deviation of 0.7 to 0.1 representing significant improvement of etch repeatability across the wafer sample.

Use of Novel Hydrofluorocarbon and Iodofluorocarbon Chemistries for a High Aspect Ratio Via Etch in a High Density Plasma Etch Tool

1998 ◽  
Vol 145 (12) ◽  
pp. 4305-4312 ◽  
Author(s):  
Simon Karecki ◽  
Laura Pruette ◽  
Rafael Reif ◽  
Terry Sparks ◽  
Laurie Beu ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
High Density ◽  
Plasma Etch ◽  
Density Plasma

Simulating the chlorine plasma etching profile of high-aspect-ratio trenches in Si

2017 ◽  
Vol 46 (5) ◽  
pp. 301-308
Author(s):  
A. S. Shumilov ◽  
I. I. Amirov ◽  
V. F. Luckichev
Keyword(s):  
Aspect Ratio ◽  
Plasma Etching ◽  
High Aspect Ratio ◽  
Etching Profile
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